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    • 3. 发明申请
    • TEST ACCESS MECHANISM FOR MULTI-CORE PROCESSOR OR OTHER INTEGRATED CIRCUIT
    • 多核处理器或其他集成电路的测试访问机制
    • US20090193303A1
    • 2009-07-30
    • US12021455
    • 2008-01-29
    • Grady L. GilesBrian HoangTimothy J. Wood
    • Grady L. GilesBrian HoangTimothy J. Wood
    • G01R31/3177G06F11/25
    • G01R31/318536G01R31/318544G01R31/318572G06F11/2236
    • A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one of the plurality of processor cores. The pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel, and a compare channel. Each pipeline stage is operable to convey commands to its corresponding processor core via the command channel, to convey scan input data to its corresponding processor core via the SDI channel, to receive scan output data conveyed from the corresponding processor core to the SDO channel and the compare channel, and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data.
    • 具有流水线测试访问机制(TAM)的处理器。 处理器包括多个处理器核心。 每个处理器核心包括包括多个串联扫描元件的扫描链。 处理器还包括流水线TAM,流水线TAM包括多个流水线级,每个流水线对应于多个处理器核心之一。 流水线TAM包括命令通道,扫描数据输入(SDI)通道,扫描数据输出(SDO)通道和比较通道。 每个流水线级可操作以经由命令通道将命令传送到其对应的处理器核心,以经由SDI信道将扫描输入数据传送到其对应的处理器核心,以接收从相应处理器核心传送到SDO通道的扫描输出数据, 比较通道,并通过比较通道向下游传送比较数据,其中比较数据基于扫描输出数据。
    • 5. 发明授权
    • Test access mechanism for multi-core processor or other integrated circuit
    • 多核处理器或其他集成电路的测试访问机制
    • US08103924B2
    • 2012-01-24
    • US12021455
    • 2008-01-29
    • Grady L. GilesBrian HoangTimothy J. Wood
    • Grady L. GilesBrian HoangTimothy J. Wood
    • G01R31/28
    • G01R31/318536G01R31/318544G01R31/318572G06F11/2236
    • A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one of the plurality of processor cores. The pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel, and a compare channel. Each pipeline stage is operable to convey commands to its corresponding processor core via the command channel, to convey scan input data to its corresponding processor core via the SDI channel, to receive scan output data conveyed from the corresponding processor core to the SDO channel and the compare channel, and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data.
    • 具有流水线测试访问机制(TAM)的处理器。 处理器包括多个处理器核心。 每个处理器核心包括包括多个串联扫描元件的扫描链。 处理器还包括流水线TAM,流水线TAM包括多个流水线级,每个流水线对应于多个处理器核心之一。 流水线TAM包括命令通道,扫描数据输入(SDI)通道,扫描数据输出(SDO)通道和比较通道。 每个流水线级可操作以经由命令通道将命令传送到其对应的处理器核心,以经由SDI信道将扫描输入数据传送到其对应的处理器核心,以接收从相应处理器核心传送到SDO通道的扫描输出数据, 比较通道,并通过比较通道向下游传送比较数据,其中比较数据基于扫描输出数据。
    • 6. 发明授权
    • Method of transferring data to multiple units operating in a lower-frequency domain
    • 将数据传送到在较低频域工作的多个单元的方法
    • US07180891B1
    • 2007-02-20
    • US10057393
    • 2002-01-25
    • Brian Hoang
    • Brian Hoang
    • H04J11/00H04L12/56H04L12/54H04L12/04
    • H04L7/02H04L7/0008
    • There is disclosed herein a multi-port frequency step-down queue that efficiently transfers data from a fast clock domain to a slow-clock domain having parallel hardware resources. In one embodiment, the queue includes a set of registers that are sequentially selected by an input counter that receives the fast clock. As the registers are selected, they store a data item from the input data stream. The queue also includes multiple multiplexers each having inputs that are sequentially selected by an output counter that receives the slow clock. The first multiplexer is coupled to the first N registers in the queue, the second multiplexer is coupled to the second N registers in the queue, etc. In this manner, the step-down queue generates multiple output FIFO data streams at the slower clock rate. Each of the output data streams may then be processed in parallel.
    • 这里公开了一种多端口频率降阶队列,其有效地将数据从快速时钟域传输到具有并行硬件资源的慢时钟域。 在一个实施例中,队列包括由接收快速时钟的输入计数器顺序选择的一组寄存器。 当选择寄存器时,它们存储来自输入数据流的数据项。 队列还包括多个多路复用器,每个多路复用器具有由接收慢时钟的输出计数器依次选择的输入。 第一复用器耦合到队列中的前N个寄存器,第二多路复用器耦合到队列中的第二N个寄存器等。以这种方式,降阶队列以较慢的时钟速率产生多个输出FIFO数据流 。 然后可以并行地处理每个输出数据流。