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1. 发明申请

US20050125755A1 Method of generating an efficient stuck-at fault and transition delay fault truncated scan test pattern for an integrated circuit design 失效
标题翻译：产生集成电路设计的有效卡住故障和转换延迟故障截断扫描测试图案的方法
公开(公告)号：US20050125755A1
公开(公告)日：2005-06-09
申请号：US10728036
申请日：2003-12-03
申请人： Cam Lu , Robert Benware , Thai Nguyen
发明人： Cam Lu , Robert Benware , Thai Nguyen
IPC分类号： G01R31/3183 , G06F11/00 , G06F17/50
CPC分类号： G01R31/318328
摘要： A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-at fault patterns to achieve maximum stuck-at fault and transition delay fault coverage; (c) truncating the estimated number of transition delay fault patterns to generate a truncated set of transition delay fault patterns so that the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns achieve maximum stuck-at fault and transition delay fault coverage within a selected scan memory limit; and (d) generating as output the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns.
摘要翻译：生成用于集成电路设计的截头扫描测试图案的方法包括以下步骤：（a）接收作为输入的集成电路设计; （b）估计过渡延迟故障测试模式的数量和相应数量的顶点卡住故障模式，以实现最大卡住故障和转换延迟故障覆盖; （c）截断估计的转移延迟故障模式数，以产生截断的一组过渡延迟故障模式，使得截断的过渡延迟故障模式集合和相应数量的最大持续故障模式实现最大卡住所选扫描存储限制内的故障和转换延迟故障覆盖; 和（d）产生截断的过渡延迟故障模式集合的输出以及相应数量的顶部卡住故障模式。

2. 发明申请

US20060095816A1 Test clocking scheme 失效
标题翻译：测试计时方案
公开(公告)号：US20060095816A1
公开(公告)日：2006-05-04
申请号：US10975315
申请日：2004-10-28
申请人： Thai Nguyen , William Shen , Cam Lu
发明人： Thai Nguyen , William Shen , Cam Lu
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G01R31/31725 , G01R31/31721 , G01R31/318575 , G01R31/318594 , G11C29/12015 , G11C29/14
摘要： A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock paths. The test clocking scheme provides for the ability to separately shut off either the memory functional clock source or the memory test clock source, provides that less power is required during production testing, and provides that simulation time is reduced during design verification because the functional logic is not clocked.
摘要翻译：测试时钟方案，将驱动功能逻辑和存储器的时钟与驱动测试逻辑和存储器的时钟进行分离。换句话说，测试时钟方案将存储器功能时钟与存储器测试时钟分离成两个时钟路径。测试时钟方案提供分开关闭存储器功能时钟源或存储器测试时钟源的能力，提供在生产测试期间需要较少的功率，并且提供在设计验证期间减少仿真时间，因为功能逻辑是没时钟

3. 发明授权

US07444560B2 Test clocking scheme 失效
标题翻译：测试计时方案
公开(公告)号：US07444560B2
公开(公告)日：2008-10-28
申请号：US10975315
申请日：2004-10-28
申请人： Thai M. Nguyen , William Shen , Cam Lu
发明人： Thai M. Nguyen , William Shen , Cam Lu
IPC分类号： G11C29/00 , G11C7/00 , G01R31/28
CPC分类号： G01R31/31725 , G01R31/31721 , G01R31/318575 , G01R31/318594 , G11C29/12015 , G11C29/14
摘要： A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock paths. The test clocking scheme provides for the ability to separately shut off either the memory functional clock source or the memory test clock source, provides that less power is required during production testing, and provides that simulation time is reduced during design verification because the functional logic is not clocked.
摘要翻译：测试时钟方案，将驱动功能逻辑和存储器的时钟与驱动测试逻辑和存储器的时钟进行分离。换句话说，测试时钟方案将存储器功能时钟与存储器测试时钟分离成两个时钟路径。测试时钟方案提供分开关闭存储器功能时钟源或存储器测试时钟源的能力，提供在生产测试期间需要较少的功率，并且提供在设计验证期间减少仿真时间，因为功能逻辑是没时钟

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