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31. 发明申请

US20090079030A1 Forming SOI Trench Memory with Single-Sided Buried Strap 失效
标题翻译：形成具有单面埋地带的SOI沟槽存储器
公开(公告)号：US20090079030A1
公开(公告)日：2009-03-26
申请号：US12169727
申请日：2008-07-09
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/02 , H01L29/92
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译：形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

32. 发明授权

US07384842B1 Methods involving silicon-on-insulator trench memory with implanted plate 有权
标题翻译：涉及具有植入板的绝缘体上硅沟槽存储器的方法
公开(公告)号：US07384842B1
公开(公告)日：2008-06-10
申请号：US12031093
申请日：2008-02-14
申请人： Kangguo Cheng , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： A method for fabricating silicon-on-insulator (SOI) trench memory includes forming a trench on a substrate, wherein a buried oxide layer is disposed on the substrate, a SOI layer is disposed on the buried oxide layer, and a hardmask layer is disposed on the SOI layer, implanting ions into the substrate and the SOI layer on a first opposing side of the trench and a second opposing side the trench to partially form a capacitor, depositing a node dielectric in the trench, filling the trench with a first polysilicon, removing a portion of the first polysilicon from the trench, removing an exposed portion of the node dielectric, filling the trench with a second polysilicon, masking to define an active region on the hardmask layer, forming shallow trench isolation (STI) such that the STI contacts a portion of the buried oxide layer, removing the hardmask layer, and forming a transistor.
摘要翻译：一种用于制造绝缘体上硅（SOI）沟槽存储器的方法，包括在衬底上形成沟槽，其中掩埋氧化物层设置在衬底上，SOI层设置在掩埋氧化物层上，并且设置硬掩模层在所述SOI层上，将离子注入到所述衬底中并且在所述沟槽的第一相对侧上的所述SOI层和所述沟槽的第二相对侧，以部分地形成电容器，在所述沟槽中沉积节点电介质，用第一多晶硅填充所述沟槽从所述沟槽去除所述第一多晶硅的一部分，去除所述节点电介质的暴露部分，用第二多晶硅填充所述沟槽，以掩蔽以限定所述硬掩模层上的有源区域，形成浅沟槽隔离（STI），使得 STI接触掩埋氧化物层的一部分，去除硬掩模层，并形成晶体管。

33. 发明申请

US20080132025A1 ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF 审中-公开
标题翻译：具有用于低基板偏移操作的薄层氧化物（盒）上的反相收集器的超薄SOI垂直双极晶体管及其方法
公开(公告)号：US20080132025A1
公开(公告)日：2008-06-05
申请号：US11877305
申请日：2007-10-23
申请人： Herbert L. Ho , Mahender Kumar , Qiqing Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
发明人： Herbert L. Ho , Mahender Kumar , Qiqing Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
IPC分类号： H01L21/331
CPC分类号： H01L29/7317
摘要： The present invention provides a “collector-less” silcon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BIJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.
摘要翻译：本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SIL）双极结型晶体管（BJT）。相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反转层。这种器件的优点是其类似CMOS的工艺。因此，可以简化集成方案，并且可以显着降低制造成本。本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BIJT的方法。双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

34. 发明授权

US07115965B2 Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation 失效
标题翻译：具有绝大多数载流子积累层的垂直双极晶体管作为用于SOI BiCMOS的子集电极，具有降低的掩埋氧化物厚度以用于低衬底偏置操作
公开(公告)号：US07115965B2
公开(公告)日：2006-10-03
申请号：US10931855
申请日：2004-09-01
申请人： Herbert L. Ho , Mahender Kumar , Qiqing Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
发明人： Herbert L. Ho , Mahender Kumar , Qiqing Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
IPC分类号： H01L29/70
CPC分类号： H01L29/7317 , H01L21/84 , H01L27/1203 , H01L29/0821 , H01L29/66265
摘要： The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.
摘要翻译：本发明提供了一种不含杂质掺杂子集电极的“不带集电极的绝缘体上硅”（SOI）双极结型晶体管（BJT）。相反，本发明的垂直SOI BJT在操作时使用背栅极多数载流子积累层作为子集电极。 SOI衬底被偏置，使得积累层形成在第一半导体层的底部。这种器件的优点是其类似CMOS的工艺。因此，可以简化集成方案，并且可以显着降低制造成本。本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。还提供了背栅CMOS装置。

35. 发明授权

US07073139B2 Method for determining cell body and biasing plate contact locations for embedded dram in SOI 失效
标题翻译：用于确定SOI中嵌入电容的电池体和偏置板接触位置的方法
公开(公告)号：US07073139B2
公开(公告)日：2006-07-04
申请号：US10250090
申请日：2003-06-03
申请人： Karen A. Bard , Herbert L. Ho
发明人： Karen A. Bard , Herbert L. Ho
IPC分类号： G06F17/50
CPC分类号： H01L27/1203 , G06F17/5068 , H01L21/84 , H01L27/0214 , H01L27/10861 , H01L27/10894
摘要： A method for determining contact location for embedded dynamic random access memory (eDRAM) formed in a silicon-on-insulator (SOI) substrate includes reviewing contact design data for an eDRAM device and discarding contact locations corresponding to contact shapes within a support area of the eDRAM device. Contact locations corresponding to bitline contacts to storage cells within the eDRAM device are saved and outputted to a custom design level to be used in forming body contacts for the eDRAM formed in the SOI substrate.
摘要翻译：一种用于确定在绝缘体上硅（SOI）衬底中形成的嵌入式动态随机存取存储器（eDRAM）的接触位置的方法，包括：检查eDRAM器件的接触设计数据，并丢弃对应于接触形状在第 eDRAM设备。与eDRAM器件内的存储单元的位线触点相对应的接触位置被保存并输出到定制设计级，以用于形成SOI衬底中形成的eDRAM的体接触。

36. 发明授权

US06429101B1 Method of forming thermally stable polycrystal to single crystal electrical contact structure 失效
标题翻译：将热稳定多晶体形成为单晶电接触结构的方法
公开(公告)号：US06429101B1
公开(公告)日：2002-08-06
申请号：US09240753
申请日：1999-01-29
申请人： Ricky S. Amos , Arne W. Ballantine , Gregory Bazan , Bomy A. Chen , Douglas D. Coolbaugh , Ramachandra Divakaruni , Heidi L. Greer , Herbert L. Ho , Joseph F. Kudlacik , Bernard P. Leroy , Paul C. Parries , Gary L. Patton
发明人： Ricky S. Amos , Arne W. Ballantine , Gregory Bazan , Bomy A. Chen , Douglas D. Coolbaugh , Ramachandra Divakaruni , Heidi L. Greer , Herbert L. Ho , Joseph F. Kudlacik , Bernard P. Leroy , Paul C. Parries , Gary L. Patton
IPC分类号： H01L2120
CPC分类号： H01L21/02126 , H01L21/0214 , H01L21/02236 , H01L21/02249 , H01L21/02255 , H01L21/31662
摘要： A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.
摘要翻译：一种形成包含单晶半导体区域和多晶半导体区域的热稳定欧姆接触结构的方法。在单晶半导体区域的至少一部分与多晶半导体区域之间形成介电材料的至少一个区域，从而控制多晶半导体的晶粒生长。

37. 发明授权

US06410399B1 Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization 失效
标题翻译：通过硅化法降低基于沟槽的DRAMS中的带，字线和位线接触电阻的工艺
公开(公告)号：US06410399B1
公开(公告)日：2002-06-25
申请号：US09606493
申请日：2000-06-29
申请人： Philip Lee Flaitz , Herbert L. Ho , Subramanian Iyer , Babar Khan , Paul C. Parries
发明人： Philip Lee Flaitz , Herbert L. Ho , Subramanian Iyer , Babar Khan , Paul C. Parries
IPC分类号： H01L2120
CPC分类号： H01L27/10867 , H01L21/28052 , H01L21/28518 , H01L21/76895 , H01L29/665
摘要： A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.
摘要翻译：一种半导体器件制造方法，用于在动态随机存取存储器（DRAMS）和嵌入式DRAM（eDRAM）器件的阵列区域中硅化硅含量区域，以降低电阻，并在低温下提高器件的可靠性。

38. 发明授权

US06340615B1 Method of forming a trench capacitor DRAM cell 失效
标题翻译：形成沟槽电容器DRAM单元的方法
公开(公告)号：US06340615B1
公开(公告)日：2002-01-22
申请号：US09466605
申请日：1999-12-17
申请人： Sundar K. Iyer , Rama Divakaruni , Herbert L. Ho , Subramanian Iyer , Babar A. Khan
发明人： Sundar K. Iyer , Rama Divakaruni , Herbert L. Ho , Subramanian Iyer , Babar A. Khan
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： A method of connecting a trench capacitor in a dynamic random access memory (DRAM) cell. First, trenches are formed in a silicon substrate using a masking layer including a pad nitride layer on a pad oxide layer. Trench capacitors are formed in the trenches. A buried strap is formed in each trench on the capacitor. The nitride pad layer is pulled back from the trench openings, exposing the pad oxide layer and any strap material that may have replaced the pad oxide layer around the trenches. The straps and trench sidewalls are doped to form a resistive connection. During a subsequent shallow trench isolation (STI) process, which involves an oxidation step, the exposed strap material on the surface of the silicon surface layer forms oxide unrestrained by pad nitride without stressing the silicon substrate.
摘要翻译：一种在动态随机存取存储器（DRAM）单元中连接沟槽电容器的方法。首先，在硅衬底中使用在衬垫氧化物层上包括衬垫氮化物层的掩模层形成沟槽。沟槽电容器形成在沟槽中。在电容器的每个沟槽中形成掩埋带。氮化物衬垫层从沟槽开口被拉回，暴露衬垫氧化物层和可能已经替换衬垫氧化物层的任何带材料围绕沟槽。带和沟槽侧壁被掺杂以形成电阻连接。在随后的涉及氧化步骤的浅沟槽隔离（STI）工艺中，硅表面层表面上的暴露的带材料形成不受衬垫氮化物束缚的氧化物，而不会压迫硅衬底。

39. 发明授权

US06319794B1 Structure and method for producing low leakage isolation devices 失效
标题翻译：用于生产低泄漏隔离装置的结构和方法
公开(公告)号：US06319794B1
公开(公告)日：2001-11-20
申请号：US09172697
申请日：1998-10-14
申请人： Hiroyuki Akatsu , Tze-Chiang Chen , Laertis Economikos , Herbert L. Ho , Richard Kleinhenz , Jack A. Mandelman , Wesley C. Natzle
发明人： Hiroyuki Akatsu , Tze-Chiang Chen , Laertis Economikos , Herbert L. Ho , Richard Kleinhenz , Jack A. Mandelman , Wesley C. Natzle
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill material. The intersection of the structure and the semiconductor surface in which it is formed, is free of silicon nitride, but the isolation structure may include a silicon nitride liner which is within the trench and recessed below the semiconductor surface.
摘要翻译：一种用于半导体器件的浅沟槽隔离结构和用于在半导体衬底内制造浅沟槽隔离器件的方法。浅沟槽隔离结构是无凹槽的，并且包括未退火的介电材料作为沟槽填充材料。其结构与其形成的半导体表面的交叉点不含氮化硅，但是隔离结构可以包括位于沟槽内并凹陷在半导体表面下方的氮化硅衬垫。

40. 发明授权

US5923971A Reliable low resistance strap for trench storage DRAM cell using selective epitaxy 失效
标题翻译：使用选择性外延的沟槽存储DRAM单元的可靠的低电阻带
公开(公告)号：US5923971A
公开(公告)日：1999-07-13
申请号：US731940
申请日：1996-10-22
申请人： Herbert L. Ho , Andre R. LeBlanc , Jack A. Mandelman , Radhika Srinivasan
发明人： Herbert L. Ho , Andre R. LeBlanc , Jack A. Mandelman , Radhika Srinivasan
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： Strap resistance, surface strap shorts and wordline capacitance can be reduced by providing a selectively grown silicon strap which tapers away from spacer nitride and has less contact with spacer nitride. In addition the strap is optionally doped with an arsenic implant which reduces resistance.
摘要翻译：通过提供选择性地生长的硅带，可以减少带状电阻，表面带短路和字线电容，该带从间隔氮化物逐渐变细并且与间隔氮化物接触较少。此外，带可选地掺杂有降低电阻的砷注入。

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