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1. 发明授权

US06429101B1 Method of forming thermally stable polycrystal to single crystal electrical contact structure 失效
标题翻译：将热稳定多晶体形成为单晶电接触结构的方法
公开(公告)号：US06429101B1
公开(公告)日：2002-08-06
申请号：US09240753
申请日：1999-01-29
申请人： Ricky S. Amos , Arne W. Ballantine , Gregory Bazan , Bomy A. Chen , Douglas D. Coolbaugh , Ramachandra Divakaruni , Heidi L. Greer , Herbert L. Ho , Joseph F. Kudlacik , Bernard P. Leroy , Paul C. Parries , Gary L. Patton
发明人： Ricky S. Amos , Arne W. Ballantine , Gregory Bazan , Bomy A. Chen , Douglas D. Coolbaugh , Ramachandra Divakaruni , Heidi L. Greer , Herbert L. Ho , Joseph F. Kudlacik , Bernard P. Leroy , Paul C. Parries , Gary L. Patton
IPC分类号： H01L2120
CPC分类号： H01L21/02126 , H01L21/0214 , H01L21/02236 , H01L21/02249 , H01L21/02255 , H01L21/31662
摘要： A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.
摘要翻译：一种形成包含单晶半导体区域和多晶半导体区域的热稳定欧姆接触结构的方法。在单晶半导体区域的至少一部分与多晶半导体区域之间形成介电材料的至少一个区域，从而控制多晶半导体的晶粒生长。

2. 发明授权

US06448590B1 Multiple threshold voltage FET using multiple work-function gate materials 失效
标题翻译：多阈值电压FET采用多功能栅极材料
公开(公告)号：US06448590B1
公开(公告)日：2002-09-10
申请号：US09695199
申请日：2000-10-24
申请人： James W. Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
发明人： James W. Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
IPC分类号： H01L2710
CPC分类号： H01L29/4916 , H01L21/82345 , H01L29/4238 , H01L29/495 , H01L29/4966 , H01L29/66666 , H01L29/7827
摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.
摘要翻译：通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。通过组合多个功能门极材料来开发多个阈值电压。栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。开发了用于多阈值电压设计的图案化线性阵列实施例。形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。栅极材料被布置成彼此靠近以适应小栅极长度设计。

3. 发明授权

US06939771B2 Discontinuous dielectric interface for bipolar transistors 失效
标题翻译：双极晶体管的不连续介质接口
公开(公告)号：US06939771B2
公开(公告)日：2005-09-06
申请号：US10653925
申请日：2003-09-04
申请人： Arne W. Ballantine , Douglas D. Coolbaugh , Jeffrey Gilbert , Joseph R. Greco , Glenn R. Miller
发明人： Arne W. Ballantine , Douglas D. Coolbaugh , Jeffrey Gilbert , Joseph R. Greco , Glenn R. Miller
IPC分类号： H01L29/73 , H01L21/314 , H01L21/318 , H01L21/328 , H01L21/331 , H01L29/08
CPC分类号： H01L29/66272 , H01L21/3144 , H01L21/3185 , H01L29/0804 , H01L29/0895
摘要： A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
摘要翻译：一种在半导体材料的两个区域之间形成至少一个界面区域的方法。在半导体材料的两个区域的至少一部分边界附近形成包含氮的介电材料的至少一个区域，从而控制界面处的电阻。

4. 发明授权

US06703283B1 Discontinuous dielectric interface for bipolar transistors 有权
标题翻译：双极晶体管的不连续介质接口
公开(公告)号：US06703283B1
公开(公告)日：2004-03-09
申请号：US09244958
申请日：1999-02-04
申请人： Arne W. Ballantine , Douglas D. Coolbaugh , Jeffrey Gilbert , Joseph R. Greco , Glenn R. Miller
发明人： Arne W. Ballantine , Douglas D. Coolbaugh , Jeffrey Gilbert , Joseph R. Greco , Glenn R. Miller
IPC分类号： H01L21331
CPC分类号： H01L29/66272 , H01L21/3144 , H01L21/3185 , H01L29/0804 , H01L29/0895
摘要： A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
摘要翻译：一种在半导体材料的两个区域之间形成至少一个界面区域的方法。在半导体材料的两个区域的至少一部分边界附近形成包含氮的介电材料的至少一个区域，从而控制界面处的电阻。

5. 发明授权

US06406962B1 Vertical trench-formed dual-gate FET device structure and method for creation 失效
标题翻译：垂直沟槽形双栅FET器件结构及其制作方法
公开(公告)号：US06406962B1
公开(公告)日：2002-06-18
申请号：US09761931
申请日：2001-01-17
申请人： Paul D. Agnello , Arne W. Ballantine , Ramachandra Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
发明人： Paul D. Agnello , Arne W. Ballantine , Ramachandra Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21336
CPC分类号： H01L29/78648 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/78642
摘要： The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.
摘要翻译：本发明涉及一种形成具有垂直沟槽形成的双栅极的一个或多个FET的装置和方法，其中多个氮化物层具有周期性地设置在其上的氧化物标记蚀刻停止层，从而使FET具有多个可选择的栅极长度。本发明提供控制和形成尺寸缩小到约5nm至约100nm，优选约5nm至约50nm的栅极长度。具有氧化物蚀刻停止层的多个衬垫氮化物层通过蚀刻衬垫氮化物层中的多个通孔来提供本FET连接到具有对应于所使用的栅极长度的各种连接深度的多个触点由此这些通孔在选定的蚀刻停止层处停止以提供适于与所选择的这些触点连接的通孔。附加的栅极材料可以沉积在所选择的多个氮化物层的顶表面上，以允许与任何给定FET的栅电极的接触。

6. 发明授权

US06797553B2 Method for making multiple threshold voltage FET using multiple work-function gate materials 有权
标题翻译：使用多功能栅极材料制造多个阈值电压FET的方法
公开(公告)号：US06797553B2
公开(公告)日：2004-09-28
申请号：US10205143
申请日：2002-07-24
申请人： James W Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
发明人： James W Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
IPC分类号： H01L218238
CPC分类号： H01L29/4916 , H01L21/82345 , H01L29/4238 , H01L29/495 , H01L29/4966 , H01L29/66666 , H01L29/7827
摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.
摘要翻译：通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。通过组合多个功能门极材料来开发多个阈值电压。栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。开发了用于多阈值电压设计的图案化线性阵列实施例。形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。栅极材料被布置成彼此靠近以适应小栅极长度设计。

7. 发明授权

US06984593B2 Beta control using a rapid thermal oxidation 有权
标题翻译： Beta控制使用快速热氧化
公开(公告)号：US06984593B2
公开(公告)日：2006-01-10
申请号：US10653912
申请日：2003-09-04
申请人： Arne W. Ballantine , Douglas D. Coolbaugh , Steve S. Williams
发明人： Arne W. Ballantine , Douglas D. Coolbaugh , Steve S. Williams
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L21/32055 , H01L29/66272 , Y10S438/981
摘要： A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C.
摘要翻译：一种形成半导体器件的方法，所述半导体器件通过在小于约700℃的温度下快速热氧化衬底表面来处理衬底的表面以产生表面上材料的不连续生长。

8. 发明授权

US06958506B2 High-dielectric constant insulators for feol capacitors 有权
标题翻译：高介电常数绝缘子
公开(公告)号：US06958506B2
公开(公告)日：2005-10-25
申请号：US10688508
申请日：2003-10-17
申请人： Evgeni P. Gousev , Harald F. Okorn-Schmidt , Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh
发明人： Evgeni P. Gousev , Harald F. Okorn-Schmidt , Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh
IPC分类号： H01L29/73 , H01L21/02 , H01L21/28 , H01L21/331 , H01L21/822 , H01L21/8222 , H01L21/8234 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/08 , H01L29/51 , H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L27/0629 , H01L27/0635 , H01L27/0805 , H01L28/55 , H01L28/60 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.
摘要翻译：提供了形成前端的方法（FEOL）电容器，例如多晶硅 - 多晶硅电容器和金属 - 绝缘体 - 硅电容器，其能够将高介电常数（k大于约8）并入电容器结构体。本发明的方法提供了用于高频响应的顶部和底部电极具有低串联电阻的高电容/面积器件。本发明的方法提供了芯片尺寸的显着降低，特别是在使用大面积电容的模拟和混合信号应用中。

9. 发明授权

US06667207B2 High-dielectric constant insulators for FEOL capacitors 失效
标题翻译：用于FEOL电容器的高介电常数绝缘子
公开(公告)号：US06667207B2
公开(公告)日：2003-12-23
申请号：US10246110
申请日：2002-09-18
申请人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh , Evgeni P. Gousev , Harald F. Okorn-Schmidt
发明人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh , Evgeni P. Gousev , Harald F. Okorn-Schmidt
IPC分类号： H01L218249
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L27/0629 , H01L27/0635 , H01L27/0805 , H01L28/55 , H01L28/60 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.
摘要翻译：提供了形成前端的方法（FEOL）电容器，例如多晶硅 - 多晶硅电容器和金属 - 绝缘体 - 硅电容器，其能够将高介电常数（k大于约8）并入电容器结构体。本发明的方法提供了用于高频响应的顶部和底部电极具有低串联电阻的高电容/面积器件。本发明的方法提供了芯片尺寸的显着降低，特别是在使用大面积电容的模拟和混合信号应用中。

10. 发明授权

US07439607B2 Beta control using a rapid thermal oxidation 有权
标题翻译： Beta控制使用快速热氧化
公开(公告)号：US07439607B2
公开(公告)日：2008-10-21
申请号：US11246298
申请日：2005-10-11
申请人： Arne W. Ballantine , Douglas D. Coolbaugh , Steve S. Williams
发明人： Arne W. Ballantine , Douglas D. Coolbaugh , Steve S. Williams
IPC分类号： H01L27/082
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L21/32055 , H01L29/66272 , Y10S438/981
摘要： A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C.
摘要翻译：一种形成半导体器件的方法，所述半导体器件通过在小于约700℃的温度下快速热氧化衬底表面来处理衬底的表面以产生表面上材料的不连续生长。

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