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31. 发明授权

US06410399B1 Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization 失效
标题翻译：通过硅化法降低基于沟槽的DRAMS中的带，字线和位线接触电阻的工艺
公开(公告)号：US06410399B1
公开(公告)日：2002-06-25
申请号：US09606493
申请日：2000-06-29
申请人： Philip Lee Flaitz , Herbert L. Ho , Subramanian Iyer , Babar Khan , Paul C. Parries
发明人： Philip Lee Flaitz , Herbert L. Ho , Subramanian Iyer , Babar Khan , Paul C. Parries
IPC分类号： H01L2120
CPC分类号： H01L27/10867 , H01L21/28052 , H01L21/28518 , H01L21/76895 , H01L29/665
摘要： A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.
摘要翻译：一种半导体器件制造方法，用于在动态随机存取存储器（DRAMS）和嵌入式DRAM（eDRAM）器件的阵列区域中硅化硅含量区域，以降低电阻，并在低温下提高器件的可靠性。

32. 发明授权

US06340615B1 Method of forming a trench capacitor DRAM cell 失效
标题翻译：形成沟槽电容器DRAM单元的方法
公开(公告)号：US06340615B1
公开(公告)日：2002-01-22
申请号：US09466605
申请日：1999-12-17
申请人： Sundar K. Iyer , Rama Divakaruni , Herbert L. Ho , Subramanian Iyer , Babar A. Khan
发明人： Sundar K. Iyer , Rama Divakaruni , Herbert L. Ho , Subramanian Iyer , Babar A. Khan
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： A method of connecting a trench capacitor in a dynamic random access memory (DRAM) cell. First, trenches are formed in a silicon substrate using a masking layer including a pad nitride layer on a pad oxide layer. Trench capacitors are formed in the trenches. A buried strap is formed in each trench on the capacitor. The nitride pad layer is pulled back from the trench openings, exposing the pad oxide layer and any strap material that may have replaced the pad oxide layer around the trenches. The straps and trench sidewalls are doped to form a resistive connection. During a subsequent shallow trench isolation (STI) process, which involves an oxidation step, the exposed strap material on the surface of the silicon surface layer forms oxide unrestrained by pad nitride without stressing the silicon substrate.
摘要翻译：一种在动态随机存取存储器（DRAM）单元中连接沟槽电容器的方法。首先，在硅衬底中使用在衬垫氧化物层上包括衬垫氮化物层的掩模层形成沟槽。沟槽电容器形成在沟槽中。在电容器的每个沟槽中形成掩埋带。氮化物衬垫层从沟槽开口被拉回，暴露衬垫氧化物层和可能已经替换衬垫氧化物层的任何带材料围绕沟槽。带和沟槽侧壁被掺杂以形成电阻连接。在随后的涉及氧化步骤的浅沟槽隔离（STI）工艺中，硅表面层表面上的暴露的带材料形成不受衬垫氮化物束缚的氧化物，而不会压迫硅衬底。

33. 发明授权

US06319794B1 Structure and method for producing low leakage isolation devices 失效
标题翻译：用于生产低泄漏隔离装置的结构和方法
公开(公告)号：US06319794B1
公开(公告)日：2001-11-20
申请号：US09172697
申请日：1998-10-14
申请人： Hiroyuki Akatsu , Tze-Chiang Chen , Laertis Economikos , Herbert L. Ho , Richard Kleinhenz , Jack A. Mandelman , Wesley C. Natzle
发明人： Hiroyuki Akatsu , Tze-Chiang Chen , Laertis Economikos , Herbert L. Ho , Richard Kleinhenz , Jack A. Mandelman , Wesley C. Natzle
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill material. The intersection of the structure and the semiconductor surface in which it is formed, is free of silicon nitride, but the isolation structure may include a silicon nitride liner which is within the trench and recessed below the semiconductor surface.
摘要翻译：一种用于半导体器件的浅沟槽隔离结构和用于在半导体衬底内制造浅沟槽隔离器件的方法。浅沟槽隔离结构是无凹槽的，并且包括未退火的介电材料作为沟槽填充材料。其结构与其形成的半导体表面的交叉点不含氮化硅，但是隔离结构可以包括位于沟槽内并凹陷在半导体表面下方的氮化硅衬垫。

34. 发明授权

US5923971A Reliable low resistance strap for trench storage DRAM cell using selective epitaxy 失效
标题翻译：使用选择性外延的沟槽存储DRAM单元的可靠的低电阻带
公开(公告)号：US5923971A
公开(公告)日：1999-07-13
申请号：US731940
申请日：1996-10-22
申请人： Herbert L. Ho , Andre R. LeBlanc , Jack A. Mandelman , Radhika Srinivasan
发明人： Herbert L. Ho , Andre R. LeBlanc , Jack A. Mandelman , Radhika Srinivasan
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： Strap resistance, surface strap shorts and wordline capacitance can be reduced by providing a selectively grown silicon strap which tapers away from spacer nitride and has less contact with spacer nitride. In addition the strap is optionally doped with an arsenic implant which reduces resistance.
摘要翻译：通过提供选择性地生长的硅带，可以减少带状电阻，表面带短路和字线电容，该带从间隔氮化物逐渐变细并且与间隔氮化物接触较少。此外，带可选地掺杂有降低电阻的砷注入。

35. 发明授权

US5670805A Controlled recrystallization of buried strap in a semiconductor memory device 失效
标题翻译：半导体存储器件中埋置带的可控再结晶
公开(公告)号：US5670805A
公开(公告)日：1997-09-23
申请号：US643983
申请日：1996-05-07
申请人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard Johannes Stengl
发明人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard Johannes Stengl
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L27/10861
摘要： A semiconductor memory device includes a trench formed in a semiconductor substrate. Conductive material is formed in the trench and is insulatively spaced from the semiconductor substrate to form a capacitor. A transfer gate transistor includes source/drain regions formed on a surface of the semiconductor substrate and a control gate which is insulatively spaced from a channel region between the source and drain regions. A buried strap electrically connects the capacitor to one of the source/drain regions of the transfer gate transistor. A portion of the buried strap includes recrystallized silicon.
摘要翻译：半导体存储器件包括形成在半导体衬底中的沟槽。导电材料形成在沟槽中并且与半导体衬底绝缘地间隔开以形成电容器。传输栅极晶体管包括形成在半导体衬底的表面上的源极/漏极区域和与源极区域和漏极区域之间的沟道区域间隔开的控制栅极。掩埋带将电容器电连接到传输栅极晶体管的源极/漏极区域之一。掩埋带的一部分包括再结晶硅。

36. 发明授权

US08877603B2 Semiconductor-on-oxide structure and method of forming 有权
标题翻译：半导体氧化物结构及其形成方法
公开(公告)号：US08877603B2
公开(公告)日：2014-11-04
申请号：US13435056
申请日：2012-03-30
申请人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
发明人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
IPC分类号： H01L21/76 , H01L21/30 , H01L21/46
CPC分类号： H01L29/06 , H01L21/76254
摘要： Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.
摘要翻译：公开了形成这种结构的半导体 - 氧化物结构和相关方法。在一种情况下，一种方法包括：在衬底上形成第一介质层; 在所述第一介电层上形成第一导电层，所述第一导电层包括金属或硅化物之一; 在所述第一导电层上形成第二电介质层; 将施主晶片键合到第二介电层，施主晶片包括施主电介质和半导体层; 切割施主晶片以去除施主半导体层的一部分; 从所述施主半导体层的未移动部分形成至少一个半导体隔离区; 以及通过施主电介质和第二介电层形成与第一导电层的接触。

37. 发明授权

US08753936B2 Changing effective work function using ion implantation during dual work function metal gate integration 有权
标题翻译：在双功能金属门集成中，使用离子注入来改变有效的功函数
公开(公告)号：US08753936B2
公开(公告)日：2014-06-17
申请号：US12190220
申请日：2008-08-12
申请人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L21/8234
CPC分类号： H01L29/49 , H01L21/28079 , H01L21/28088 , H01L21/823842 , H01L27/092 , H01L29/4958 , H01L29/517
摘要： Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.
摘要翻译：提出了离子注入来改变双功能金属栅极整合的有效功函数。一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。

38. 发明申请

US20130256830A1 SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING 有权
标题翻译：半导体氧化物结构及其形成方法
公开(公告)号：US20130256830A1
公开(公告)日：2013-10-03
申请号：US13435056
申请日：2012-03-30
申请人： John E. Barth, JR. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
发明人： John E. Barth, JR. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
IPC分类号： H01L23/532 , H01L21/768 , H01L29/06 , H01L21/762
CPC分类号： H01L29/06 , H01L21/76254
摘要： Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.
摘要翻译：公开了形成这种结构的半导体 - 氧化物结构和相关方法。在一种情况下，一种方法包括：在衬底上形成第一介质层; 在所述第一介电层上形成第一导电层，所述第一导电层包括金属或硅化物之一; 在所述第一导电层上形成第二电介质层; 将施主晶片键合到第二介电层，施主晶片包括施主电介质和半导体层; 切割施主晶片以去除施主半导体层的一部分; 从所述施主半导体层的未移动部分形成至少一个半导体隔离区; 以及通过施主电介质和第二介电层形成与第一导电层的接触。

39. 发明申请

US20120175694A1 STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
标题翻译：形成增强板阵列隔离装置的结构和方法
公开(公告)号：US20120175694A1
公开(公告)日：2012-07-12
申请号：US13408187
申请日：2012-02-29
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.
摘要翻译：提供了一种存储器件，其包括绝缘体上半导体（SOI）衬底，其包括位于掩埋介电层顶部的第一半导体层，其中所述掩埋介电层覆盖在第二半导体层上。电容器存在于沟槽中，其中沟槽从第一半导体层的上表面延伸穿过埋入介质层并延伸到第二半导体层。保护性氧化物存在于位于第一半导体层附近的空隙中，并且传导晶体管存在于与电容器电连通的绝缘体上半导体衬底上。

40. 发明授权

US08120095B2 High-density, trench-based non-volatile random access SONOS memory SOC applications 有权
标题翻译：高密度，基于沟槽的非易失性随机存取SONOS存储器SOC应用
公开(公告)号：US08120095B2
公开(公告)日：2012-02-21
申请号：US11955940
申请日：2007-12-13
申请人： Herbert L. Ho , Jack A. Mandelman , Tak H. Ning , Yoichi Otani
发明人： Herbert L. Ho , Jack A. Mandelman , Tak H. Ning , Yoichi Otani
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , G11C16/0433 , H01L27/11565 , H01L27/1157
摘要： The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine readable medium. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 μm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.
摘要翻译：本发明提供了具有可随机存取的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元，以及包括体现在机器可读介质中的半导体存储器件的设计结构。在一个实施例中，提供了2-Tr SONOS单元，其中选择晶体管位于具有1至2μm的沟槽深度的沟槽结构，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

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