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1. 发明授权

US6054345A Method for forming deep depletion mode dynamic random access memory (DRAM) cell 失效
标题翻译：形成深耗尽型动态随机存取存储器（DRAM）单元的方法
公开(公告)号：US6054345A
公开(公告)日：2000-04-25
申请号：US833557
申请日：1997-04-07
申请人： Johann Alsmeier , Reinhard Johannes Stengl
发明人： Johann Alsmeier , Reinhard Johannes Stengl
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/108
摘要： A semiconductor memory device for receiving a charge, includes a substrate, a transfer gate overlying the substrate, a storage device coupled to the transfer gate, a deep depleted region formed in the substrate under the storage means, and a bit line for initially receiving the charge and the substrate receiving the charge via the transfer gate. The substrate is highly resistive in a deep depletion mode, if no charge is stored therein, and has a relatively low resistivity in a charged state. Further, a process of forming a semiconductor memory device, includes depositing a first gate oxide over a substrate having a trench and depositing a nitride over the first gate oxide, forming openings in the nitride down to the gate oxide, and depositing polysilicon over the nitride and etching first spacers in the polysilicon along the sidewalls of the openings in the nitride. A second polysilicon material is deposited over the first spacers and substrate and second spacers are formed in the second polysilicon material. A contact window is opened between first and second ones of the first spacers and a highly doped polysilicon is deposited in the contact window. A contact is formed over the highly doped polysilicon.
摘要翻译：一种用于接收电荷的半导体存储器件，包括衬底，覆盖衬底的传输栅极，耦合到传输栅极的存储器件，形成在存储器件下方的衬底中的深度耗尽区域，以及用于初始接收电荷和基板通过传输门接收电荷。如果在其中不存储电荷并且在充电状态下具有相对低的电阻率，则衬底在深度耗尽模式下是高电阻的。此外，形成半导体存储器件的过程包括在具有沟槽的衬底上沉积第一栅极氧化物，并在第一栅极氧化物上沉积氮化物，在氮化物中形成栅极氧化物的开口，以及在氮化物上沉积多晶硅并且沿着氮化物中的开口的侧壁蚀刻多晶硅中的第一间隔物。在第一间隔物和衬底上沉积第二多晶硅材料，并且在第二多晶硅材料中形成第二间隔物。接触窗口在第一和第二间隔物之间打开，并且高度掺杂的多晶硅沉积在接触窗口中。在高掺杂多晶硅上形成接触。

2. 发明授权

US5960318A Borderless contact etch process with sidewall spacer and selective isotropic etch process 失效
标题翻译：无边界接触蚀刻工艺与侧壁间隔和选择性各向同性蚀刻工艺
公开(公告)号：US5960318A
公开(公告)日：1999-09-28
申请号：US549884
申请日：1995-10-27
申请人： Matthias L. Peschke , Jeffrey Gambino , James Gardner Ryan , Reinhard Johannes Stengl
发明人： Matthias L. Peschke , Jeffrey Gambino , James Gardner Ryan , Reinhard Johannes Stengl
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/76816
摘要： A method of fabricating a self-aligned borderless contact in a semiconductor device. The semiconductor device includes a first conductor level, a patterned conductor level defining a pair of spaced apart conducting segments, and a dielectric insulating layer disposed between the first conductor level and the patterned conductor level, and over the pair of spaced apart conducting segments of the patterned conductor level. The method comprises the steps of etching a contact hole in a selected region of the dielectric insulating layer which lies above and is substantially aligned between the pair of the segments. The etching continues through the dielectric insulating layer so that a portion of the dielectric insulating layer remains between the contact hole and the first conductor level. A spacer is formed which lines the contact hole. The remaining portion of the insulating layer which extends between the contact hole and the first conductor level is then etched to extend the contact hole to the first conductor level. The spacer substantially prevents the erosion of the pair of spaced apart segments during the etching of the remaining portion of the insulating layer. The contact hole is then filled with a conductive material to form the self-aligned borderless contact. The borderless contact formed by the present method is electrically isolated from the pair of spaced apart conducting segments of the patterned conductor level by the dielectric insulating layer.
摘要翻译：一种在半导体器件中制造自对准无边界接触的方法。半导体器件包括第一导体电平，限定一对间隔开的导电段的图案化导体电平，以及设置在第一导体电平和图案化导体电平之间的电介质绝缘层，以及位于所述第一导体水平的一对间隔开的导电段图案导体水平。该方法包括以下步骤：蚀刻介于绝缘层的选定区域中的接触孔，所述接触孔位于所述一对部分之间并且基本上对齐在所述一对部分之间。蚀刻继续通过介电绝缘层，使得介电绝缘层的一部分保留在接触孔和第一导体水平之间。形成了使接触孔对准的间隔物。然后蚀刻在接触孔和第一导体层之间延伸的绝缘层的剩余部分，以将接触孔延伸到第一导体水平。在绝缘层的剩余部分的蚀刻期间，间隔件基本上防止了一对间隔开的段的腐蚀。然后用导电材料填充接触孔以形成自对准的无边界接触。通过本方法形成的无边界接触通过介电绝缘层与图案化导体层的一对间隔开的导电段电隔离。

3. 发明授权

US5670805A Controlled recrystallization of buried strap in a semiconductor memory device 失效
标题翻译：半导体存储器件中埋置带的可控再结晶
公开(公告)号：US5670805A
公开(公告)日：1997-09-23
申请号：US643983
申请日：1996-05-07
申请人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard Johannes Stengl
发明人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard Johannes Stengl
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L27/10861
摘要： A semiconductor memory device includes a trench formed in a semiconductor substrate. Conductive material is formed in the trench and is insulatively spaced from the semiconductor substrate to form a capacitor. A transfer gate transistor includes source/drain regions formed on a surface of the semiconductor substrate and a control gate which is insulatively spaced from a channel region between the source and drain regions. A buried strap electrically connects the capacitor to one of the source/drain regions of the transfer gate transistor. A portion of the buried strap includes recrystallized silicon.
摘要翻译：半导体存储器件包括形成在半导体衬底中的沟槽。导电材料形成在沟槽中并且与半导体衬底绝缘地间隔开以形成电容器。传输栅极晶体管包括形成在半导体衬底的表面上的源极/漏极区域和与源极区域和漏极区域之间的沟道区域间隔开的控制栅极。掩埋带将电容器电连接到传输栅极晶体管的源极/漏极区域之一。掩埋带的一部分包括再结晶硅。

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