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31. 发明授权

US08158481B2 CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials 有权
标题翻译： CMOS结构及其制造方法，使用多个晶体取向和栅极材料
公开(公告)号：US08158481B2
公开(公告)日：2012-04-17
申请号：US12683535
申请日：2010-01-07
申请人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/8234
CPC分类号： H01L21/28079 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/6659
摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
摘要翻译：制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。平坦化层位于第二栅极材料层上。平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。也可以在第一栅极叠层上形成蚀刻停止层。所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

32. 发明授权

US07833849B2 Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode 有权
标题翻译：一种制造半导体结构的方法，包括一个器件区域，该器件区域具有位于薄化的多晶硅电极顶部的金属栅电极
公开(公告)号：US07833849B2
公开(公告)日：2010-11-16
申请号：US11323564
申请日：2005-12-30
申请人： Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Young-Hee Kim , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen , Ying Zhang
发明人： Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Young-Hee Kim , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen , Ying Zhang
IPC分类号： H01L21/62
CPC分类号： H01L21/823857 , H01L21/28044 , H01L21/28088 , H01L21/823842 , H01L29/4925 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A method of fabricating semiconductor structure is provided in which at least one nFET device and a least one pFET device are formed on a semiconductor substrate. Each device region formed includes a dielectric stack that has a net dielectric constant equal to or greater than silicon dioxide. Gate stacks are provided on each of the dielectric stacks, wherein one of the gate stacks includes a metal gate electrode located atop a surface of a thinned polygate electrode.
摘要翻译：提供一种制造半导体结构的方法，其中至少一个nFET器件和至少一个pFET器件形成在半导体衬底上。形成的每个器件区域包括具有等于或大于二氧化硅的净介电常数的电介质叠层。在每个电介质堆叠上设置栅极堆叠，其中栅极堆叠中的一个包括位于变薄的多晶硅电极的表面顶部的金属栅电极。

33. 发明申请

US20070278586A1 CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials 失效
标题翻译： CMOS结构及其制造方法，使用多个晶体取向和栅极材料
公开(公告)号：US20070278586A1
公开(公告)日：2007-12-06
申请号：US11444011
申请日：2006-05-31
申请人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L29/94
CPC分类号： H01L21/28079 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/6659
摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
摘要翻译：制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。平坦化层位于第二栅极材料层上。平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。也可以在第一栅极叠层上形成蚀刻停止层。所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

34. 发明授权

US07084460B2 Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates 有权
公开(公告)号：US07084460B2
公开(公告)日：2006-08-01
申请号：US10700085
申请日：2003-11-03
申请人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L29/12 , H01L31/036 , H01L71/01 , H01L71/12 , H01L31/039
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

35. 发明申请

US20060105559A1 Ultrathin buried insulators in Si or Si-containing material 审中-公开
标题翻译：超薄绝缘子在Si或含Si材料中
公开(公告)号：US20060105559A1
公开(公告)日：2006-05-18
申请号：US10990300
申请日：2004-11-15
申请人： Tze-Chiang Chen , Bernard Meyerson , Devendra Sadana
发明人： Tze-Chiang Chen , Bernard Meyerson , Devendra Sadana
IPC分类号： H01L21/44
CPC分类号： H01L21/76243 , H01L21/31662
摘要： A method for forming an ultra thin buried oxide layer is described incorporating the steps of forming a first epitaxial layer containing Si on a Si containing substrate having a thickness from about 10 to about 300 angstroms thick, forming a second epitaxial layer containing Si having a thickness from about 100 angstroms to about 1 micron and annealing the substrate at a temperature from 1200° C. to 1400°0 C. in an oxygen containing atmosphere. The invention over comes the problem of the buried oxide breaking up into oxide islands during the anneal.
摘要翻译：描述了一种用于形成超薄掩埋氧化物层的方法，其包括以下步骤：在厚度约10至约300埃厚的含硅衬底上形成含有Si的第一外延层，形成含有Si厚度的第二外延层从约100埃至约1微米，并在含氧气氛中在1200℃至1400℃的温度下退火底物。本发明是在退火期间埋入氧化物分解成氧化物岛的问题。

36. 发明授权

US06593205B1 Patterned SOI by formation and annihilation of buried oxide regions during processing 有权
标题翻译：在加工期间通过掩埋氧化物区域的形成和湮灭的图案化SOI
公开(公告)号：US06593205B1
公开(公告)日：2003-07-15
申请号：US10080804
申请日：2002-02-21
申请人： Tze-chiang Chen , Devendra K. Sadana
发明人： Tze-chiang Chen , Devendra K. Sadana
IPC分类号： H01L2176
CPC分类号： H01L21/76243
摘要： A method of fabricating a silicon-on-insulator (SOI) substrate including at least one patterned buried oxide region having well defined edges is provided. The method includes a step of implanting first ions into a surface of a Si-containing substrate so as to form an implant region of the first ions in the Si-containing substrate. Following the first implant step, a selective implant process is employed wherein second ions that are insoluble in SiO2 are incorporated into portions of the Si-containing substrate. The second ions employed in the selective implant step are capable of preventing the implant region of first ions from forming an oxide region during a subsequent annealing step. An annealing step is then performed which causes formation of a buried oxide region in the implant region of first ions that does not include the second ions.
摘要翻译：提供了一种制造绝缘体上硅（SOI）衬底的方法，其包括至少一个具有良好限定边缘的图案化掩埋氧化物区域。该方法包括将第一离子注入含Si衬底的表面以便在含Si衬底中形成第一离子的注入区的步骤。在第一注入步骤之后，使用选择性注入工艺，其中不溶于SiO 2的第二离子被并入含Si衬底的部分中。在选择性注入步骤中使用的第二离子能够在随后的退火步骤期间防止第一离子的注入区域形成氧化物区域。然后执行退火步骤，其导致在不包括第二离子的第一离子的注入区域中形成掩埋氧化物区域。

37. 发明授权

US06194736B1 Quantum conductive recrystallization barrier layers 失效
标题翻译：量子导电重结晶阻挡层
公开(公告)号：US06194736B1
公开(公告)日：2001-02-27
申请号：US09213674
申请日：1998-12-17
申请人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
发明人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
IPC分类号： H01L2906
CPC分类号： H01L29/66181 , H01L21/02667 , H01L21/2022 , H01L27/10867
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用量子传导重结晶阻挡层，能够实现提高可靠性和/或增加组合选择的缩小结构。量子导电层优选用于沟槽电容器中以用作再结晶屏障。

38. 发明授权

US6025639A Crack stops 失效
标题翻译：裂缝停止
公开(公告)号：US6025639A
公开(公告)日：2000-02-15
申请号：US61538
申请日：1998-04-16
申请人： Alexander R. Mitwalsky , Tze-Chiang Chen
发明人： Alexander R. Mitwalsky , Tze-Chiang Chen
IPC分类号： H01L21/301 , H01L21/78 , H01L23/544
CPC分类号： H01L21/78
摘要： Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip edges. The discontinuities can result in increasing and/or decreasing the thickness of the dielectric layer.
摘要翻译：描述了用于基本上防止沿着切割通道产生的裂纹的裂纹停止扩散到IC的有源区域。通过在芯片边缘附近的切割通道中的介电层的厚度产生不连续性来形成裂纹停止。不连续性可导致电介质层的厚度增加和/或减小。

39. 发明授权

US5789302A Crack stops 失效
公开(公告)号：US5789302A
公开(公告)日：1998-08-04
申请号：US823668
申请日：1997-03-24
申请人： Alexander R. Mitwalsky , Tze-Chiang Chen
发明人： Alexander R. Mitwalsky , Tze-Chiang Chen
IPC分类号： H01L21/301 , H01L21/78 , H01L21/46
CPC分类号： H01L21/78
摘要： Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip edges. The discontinuities can result in increasing and/or decreasing the thickness of the dielectric layer.

40. 发明申请

US20130221373A1 SOLAR CELL MADE USING A BARRIER LAYER BETWEEN P-TYPE AND INTRINSIC LAYERS 有权
标题翻译：太阳能电池使用P型和内部层之间的障碍层
公开(公告)号：US20130221373A1
公开(公告)日：2013-08-29
申请号：US13406815
申请日：2012-02-28
申请人： Tze-Chiang Chen , Augustin J. Hong , Chien-Chih Huang , Yu-Wei Huang , Jeehwan Kim , Devendra K. Sadana , Chih-Fu Tseng
发明人： Tze-Chiang Chen , Augustin J. Hong , Chien-Chih Huang , Yu-Wei Huang , Jeehwan Kim , Devendra K. Sadana , Chih-Fu Tseng
IPC分类号： H01L31/028 , H01L31/18
CPC分类号： H01L31/075 , H01L31/022466 , H01L31/1804 , H01L31/1884 , H01L31/202 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： A method for forming a photovoltaic device includes depositing a p-type layer on a substrate. A barrier layer is formed on the p-type layer by exposing the p-type layer to an oxidizing agent. An intrinsic layer is formed on the barrier layer, and an n-type layer is formed on the intrinsic layer.
摘要翻译：一种用于形成光伏器件的方法包括在衬底上沉积p型层。通过将p型层暴露于氧化剂，在p型层上形成阻挡层。在势垒层上形成本征层，在本征层上形成n型层。

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