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1. 发明授权

US06194736B1 Quantum conductive recrystallization barrier layers 失效
标题翻译：量子导电重结晶阻挡层
公开(公告)号：US06194736B1
公开(公告)日：2001-02-27
申请号：US09213674
申请日：1998-12-17
申请人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
发明人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
IPC分类号： H01L2906
CPC分类号： H01L29/66181 , H01L21/02667 , H01L21/2022 , H01L27/10867
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用量子传导重结晶阻挡层，能够实现提高可靠性和/或增加组合选择的缩小结构。量子导电层优选用于沟槽电容器中以用作再结晶屏障。

2. 发明授权

US06399434B1 Doped structures containing diffusion barriers 失效
标题翻译：含有扩散阻挡层的掺杂结构
公开(公告)号：US06399434B1
公开(公告)日：2002-06-04
申请号：US09559880
申请日：2000-04-26
申请人： Susan E. Chaloux , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Christopher C. Parks , Paul Parries , Paul A. Ronsheim , Jean-Marc Rousseau
发明人： Susan E. Chaloux , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Christopher C. Parks , Paul Parries , Paul A. Ronsheim , Jean-Marc Rousseau
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L21/28512
摘要： Semiconductor structures having improved dopant configurations are obtained by use of barrier layers containing silicon, nitrogen, and oxygen atoms and having a thickness of about 5 to 50 Å. A doped semiconductor structure with controlled dopant configuration can be formed by: (a) providing a first semiconductor material region, (b) forming an interface layer comprising silicon, oxygen, and nitrogen on the first region, (c) forming a second semiconductor material region on the interface layer, the second semiconductor material region being on an opposite side of the interface layer from the first semiconductor material region, (d) providing a dopant in the second region, and (e) heating the first and second regions whereby at least a portion of the dopant diffuses from the second region through the interface layer to the first region.
摘要翻译：具有改进的掺杂剂构型的半导体结构通过使用包含硅，氮和氧原子并且具有约5至约50埃的厚度的阻挡层来获得。具有受控掺杂剂配置的掺杂半导体结构可以通过以下方式形成：（a）提供第一半导体材料区域，（b）在第一区域上形成包含硅，氧和氮的界面层，（c）形成第二半导体材料区域，所述第二半导体材料区域在与所述第一半导体材料区域的所述界面层的相对侧上，（d）在所述第二区域中提供掺杂剂，以及（e）加热所述第一区域和所述第二区域，掺杂剂的至少一部分从第二区域扩散通过界面层到第一区域。

3. 发明授权

US06635517B2 Use of disposable spacer to introduce gettering in SOI layer 有权
标题翻译：使用一次性间隔物在SOI层中引入吸气
公开(公告)号：US06635517B2
公开(公告)日：2003-10-21
申请号：US09924014
申请日：2001-08-07
申请人： Tze-Chiang Chen , Thomas T. Hwang , Mukesh V. Khare , Effendi Leobandung , Anda C. Mocuta , Paul A. Ronsheim , Ghavam G. Shahidi
发明人： Tze-Chiang Chen , Thomas T. Hwang , Mukesh V. Khare , Effendi Leobandung , Anda C. Mocuta , Paul A. Ronsheim , Ghavam G. Shahidi
IPC分类号： H01L21335
CPC分类号： H01L29/66772 , H01L21/26506 , H01L21/3226 , H01L29/78654
摘要： A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.
摘要翻译：提供了在SOI衬底内形成自对准吸气区域的方法。具体地，本发明的方法包括以下步骤：在图案化的栅极堆叠区域的每个垂直侧壁上形成一次性间隔物，所述图案化栅极堆叠区域形成在SOI衬底的顶部含Si层上; 将吸气物质注入到不被一次性间隔物和图案化的栅堆叠区域保护的顶部含Si层中; 以及去除一次性间隔物并退火植入的吸气物质，以便将所述物种转化成吸气区域。

4. 发明授权

US6114257A Process for modified oxidation of a semiconductor substrate using chlorine plasma 失效
标题翻译：使用氯等离子体改性氧化半导体衬底的方法
公开(公告)号：US6114257A
公开(公告)日：2000-09-05
申请号：US153986
申请日：1998-09-16
申请人： Paul A. Ronsheim
发明人： Paul A. Ronsheim
IPC分类号： H01L21/324 , H01L21/306 , H01L21/316 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02046 , H01L21/02238 , H01L21/02255 , H01L21/02315 , H01L21/31662
摘要： A process for thermal oxidation of a semiconductor substrate comprising exposing the substrate to a chlorine plasma, and then heating the substrate in an oxidizing ambient. The substrate may comprise silicon, germanium, or a combination thereof. The heating step may further comprise heating at a temperature of between about 750.degree. C. and about 850.degree. C.
摘要翻译：一种半导体衬底的热氧化方法，包括将衬底暴露于氯等离子体，然后在氧化环境中加热衬底。衬底可以包括硅，锗或其组合。加热步骤还可以包括在约750℃至约850℃的温度下加热

5. 发明申请

US20130330843A1 METHOD OF MANUFACTURING SCALED EQUIVALENT OXIDE THICKNESS GATE STACKS IN SEMICONDUCTOR DEVICES AND RELATED DESIGN STRUCTURE 有权
标题翻译：半导体器件中制造等效氧化物厚度栅极堆叠的方法及相关设计结构
公开(公告)号：US20130330843A1
公开(公告)日：2013-12-12
申请号：US13490740
申请日：2012-06-07
申请人： Michael P. Chudzik , Min Dai , Jinping Liu , Paul A. Ronsheim , Joseph F. Shepard, JR. , Shahab Siddiqui
发明人： Michael P. Chudzik , Min Dai , Jinping Liu , Paul A. Ronsheim , Joseph F. Shepard, JR. , Shahab Siddiqui
IPC分类号： H01L21/66 , G06F17/50
CPC分类号： H01L29/513 , H01L21/28185 , H01L21/28202 , H01L22/12 , H01L22/26 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.
摘要翻译：公开了一种形成半导体器件的方法。该方法包括：在基板上形成电介质区域; 在包括氨（NH 3）在内的环境中退火电介质区域; 在退火期间监测所述衬底和所述电介质区域中的至少一个的氮峰; 并根据氮峰的监测来调整环境参数。

6. 发明授权

US06329704B1 Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer 失效
标题翻译：在介电层内具有峰值浓度的超浅结掺杂剂层
公开(公告)号：US06329704B1
公开(公告)日：2001-12-11
申请号：US09458530
申请日：1999-12-09
申请人： Hiroyuki Akatsu , Omer H. Dokumaci , Suryanarayan G. Hegde , Yujun Li , Rajesh Rengarajan , Paul A. Ronsheim
发明人： Hiroyuki Akatsu , Omer H. Dokumaci , Suryanarayan G. Hegde , Yujun Li , Rajesh Rengarajan , Paul A. Ronsheim
IPC分类号： H01L29167
CPC分类号： H01L21/2652 , H01L21/2254 , H01L21/2255 , H01L29/6659
摘要： A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.
摘要翻译：一种用于在硅衬底内形成超浅结深度掺杂区的工艺。该方法包括在衬底上形成电介质膜，然后将离子掺杂剂物质注入结构中。植入物种的轮廓包括通过电介质膜注入硅衬底中的群体，以及刻意限制在电介质膜中的接近于介电膜和硅衬底之间界面的峰值浓度。使用高能量，低剂量的植入工艺，并且产生基本上不含位错环和其它缺陷簇的结构。使用退火工艺来驱动更接近界面的峰值浓度，以及从电介质膜到硅衬底的最初注入物质的一些群体。由于植入的峰浓度与界面的接近以及通过电介质膜注入并进入衬底的物质的存在，维持了低热量预算。

7. 发明授权

US5194397A Method for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interface 失效
标题翻译：在多晶/单晶硅界面处理界面氧化物的方法
公开(公告)号：US5194397A
公开(公告)日：1993-03-16
申请号：US710498
申请日：1991-06-05
申请人： Robert K. Cook , Ronald W. Knepper , Subodh K. Kulkarni , Russell C. Lange , Paul A. Ronsheim , Seshadri Subbanna , Manu J. Tejwani , Bob H. Yun
发明人： Robert K. Cook , Ronald W. Knepper , Subodh K. Kulkarni , Russell C. Lange , Paul A. Ronsheim , Seshadri Subbanna , Manu J. Tejwani , Bob H. Yun
IPC分类号： H01L21/205 , H01L21/225 , H01L21/285 , H01L21/316 , H01L21/331 , H01L29/73 , H01L29/732
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02307 , H01L21/2256 , H01L21/28525 , H01L21/31662 , Y10S148/017 , Y10S148/124 , Y10S438/974
摘要： A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.

8. 发明申请

US20130052801A1 METHOD TO ENABLE COMPRESSIVELY STRAINED PFET CHANNEL IN A FINFET STRUCTURE BY IMPLANT AND THERMAL DIFFUSION 有权
标题翻译：通过植入和热扩散在FinFET结构中实现压缩应变PFET通道的方法
公开(公告)号：US20130052801A1
公开(公告)日：2013-02-28
申请号：US13221198
申请日：2011-08-30
申请人： Nathaniel C. Berliner , Pranita Kulkarni , Nicolas Loubet , Kingsuk Maitra , Sanjay C. Mehta , Paul A. Ronsheim , Toyoji Yamamoto , Zhengmao Zhu
发明人： Nathaniel C. Berliner , Pranita Kulkarni , Nicolas Loubet , Kingsuk Maitra , Sanjay C. Mehta , Paul A. Ronsheim , Toyoji Yamamoto , Zhengmao Zhu
IPC分类号： H01L21/326
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7848
摘要： A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.
摘要翻译：制造半导体器件的方法在pFET区域中形成第一鳍，并且在nFET区域中形成第二鳍。包含应变材料的多个保形微层沉积在第一和第二鳍片上。在第一翅片上形成保护盖材料，并且从第二翅片选择性地去除保形层。然后将应变材料热扩散到第一鳍中。在热退火之后以及在从第二散热片选择性地去除保形微层之后，从第一散热片上去除保护帽材料。

9. 发明申请

US20120190216A1 ANNEALING TECHNIQUES FOR HIGH PERFORMANCE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE FABRICATION 审中-公开
标题翻译：高性能补充金属氧化物半导体（CMOS）器件制造的退火技术
公开(公告)号：US20120190216A1
公开(公告)日：2012-07-26
申请号：US13097931
申请日：2011-04-29
申请人： Kevin K. Chan , Eric C. Harley , Isaac Lauer , Kam-Leung Lee , Paul A. Ronsheim
发明人： Kevin K. Chan , Eric C. Harley , Isaac Lauer , Kam-Leung Lee , Paul A. Ronsheim
IPC分类号： H01L21/268 , B82Y40/00
CPC分类号： H01L21/268 , B82Y30/00 , H01L21/823412 , H01L21/823418 , H01L27/1203 , H01L29/7833 , H01L29/7847 , H01L29/7848
摘要： A semiconductor structure is provided. In some cases, an absorber having a low deposition temperature is applied to at least a portion of the structure. At least a portion of the structure is subjected to a long flash anneal process.
摘要翻译：提供半导体结构。在一些情况下，将至少一部分结构施加具有低沉积温度的吸收体。该结构的至少一部分经历长的闪光退火工艺。

10. 发明授权

US08114748B2 Shallow extension regions having abrupt extension junctions 失效
标题翻译：浅延伸区域具有突然的延伸接头
公开(公告)号：US08114748B2
公开(公告)日：2012-02-14
申请号：US12491819
申请日：2009-06-25
申请人： Kam-Leung Lee , Paul A. Ronsheim
发明人： Kam-Leung Lee , Paul A. Ronsheim
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/26513 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200° C. to 1400° C., and a hold time period ranging from 1 millisecond to 5 milliseconds.
摘要翻译：提供一种形成半导体器件的方法，其包括在衬底顶部形成栅极结构并将衬底中的掺杂剂从衬底的上表面注入到10nm或更小的深度。在随后的步骤中，以1200℃至1400℃的峰值温度和1毫秒至5毫秒的保持时间段进行退火。

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