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21. 发明申请

US20120195106A1 SRAM Timing Cell Apparatus and Methods 有权
标题翻译： SRAM定时单元设备和方法
公开(公告)号：US20120195106A1
公开(公告)日：2012-08-02
申请号：US13017793
申请日：2011-01-31
申请人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
发明人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
IPC分类号： G11C11/40 , G11C7/06
CPC分类号： G11C7/227 , G11C11/418
摘要： Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.
摘要翻译：公开了用于提供SRAM定时跟踪单元电路的装置和方法。在一个实施例中，一种装置包括一个SRAM阵列，它包括排列成行和列的静态随机存取存储单元; 多条字线，每条字线都沿着一条行与存储器单元耦合; 用于输出时钟信号的时钟发生电路; 字线生成电路，用于响应于所述时钟信号中的一个生成在所述多个字线上的脉冲，并响应于所述时钟信号之一来终止所述脉冲; 以及跟踪单元，用于接收时钟信号并用于在SRAM跟踪时间之后将时钟产生电路输出字线脉冲结束信号; 其中所述跟踪单元还包括位于所述SRAM阵列中并且串联耦合的SRAM跟踪电路，以提供指示所述SRAM跟踪时间的信号。公开了SRAM定时的方法。

22. 发明授权

US07952939B2 Circuit and method for VDD-tracking CVDD voltage supply 有权
标题翻译：用于VDD跟踪CVDD电压源的电路和方法
公开(公告)号：US07952939B2
公开(公告)日：2011-05-31
申请号：US12205243
申请日：2008-09-05
申请人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou
发明人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/147
摘要： Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage.
摘要翻译：用于向SRAM阵列中的单元提供CVDD电源同时保持期望的VDD电压的电路和方法。描述了用于跟踪VDD电源电压并为SRAM单元提供CVDD电源的电路，其保持高于VDD的偏移，直到达到CVDD电压的最大电压。 CVDD电压为SRAM阵列中的字线驱动器和单元供电，而位线预充电和其余电路在VDD电源上工作。通过保持电压CVDD和电源电压VDD之间的最大偏移，SRAM将具有用于可靠运行的所需静态噪声容限，同时也可获得降低的VDD_min电压。公开了一种向SRAM单元阵列提供CVDD电压的方法，其中CVDD电压跟踪VDD电源电压加上预定的偏移电压。

23. 发明授权

US08559251B2 Memory circuit and method of writing datum to memory circuit 有权
标题翻译：存储电路和将数据写入存储电路的方法
公开(公告)号：US08559251B2
公开(公告)日：2013-10-15
申请号：US13354884
申请日：2012-01-20
申请人： Chih-Yu Lin , Wei Min Chan , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Chih-Yu Lin , Wei Min Chan , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G11C7/10
CPC分类号： G11C11/419
摘要： A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node.
摘要翻译：电路包括第一节点，第二节点，存储器单元，第一数据线，第二数据线和写驱动器。存储器单元耦合到第一节点和第二节点，并由第一节点处的第一电压和第二节点处的第二电压供电。第一数据线和第二数据线耦合到存储器单元。写入驱动器具有在写入操作期间承载小于第一电压的第三电压的第三节点。写引导器耦合到第一数据线和第二数据线，并且被配置为在写操作期间，选择性地将第一数据线和第二数据线之一耦合到第三节点，并将第一数据中的另一个耦合线和第二条数据线到第一个节点。

24. 发明申请

US20120327704A1 SEMICONDUCTOR MEMORIES 有权
标题翻译：半导体记忆
公开(公告)号：US20120327704A1
公开(公告)日：2012-12-27
申请号：US13164807
申请日：2011-06-21
申请人： Wei Min CHAN , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
发明人： Wei Min CHAN , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.
摘要翻译：半导体存储器包括具有形成锁存器的第一和反相器的位单元。第一和第二晶体管分别耦合到锁存器的第一和第二存储节点以及第一和第二写入位线。第一和第二晶体管中的每一个具有耦合到第一节点的相应栅极。第三和第四晶体管在第一节点处串联耦合在一起，并且设置在写入字线和第一电压源之间。第一和第二晶体管中的每一个具有耦合到第一控制线的相应栅极。第五晶体管具有耦合到第二电压源的源极，耦合到锁存器的至少一个反相器的漏极和耦合到第一节点的栅极。读端口耦合到第一读位线和锁存器的第二存储节点。

25. 发明授权

US08477527B2 SRAM timing cell apparatus and methods 有权
标题翻译： SRAM定时单元装置和方法
公开(公告)号：US08477527B2
公开(公告)日：2013-07-02
申请号：US13017793
申请日：2011-01-31
申请人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
发明人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C7/227 , G11C11/418
摘要： Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.
摘要翻译：公开了用于提供SRAM定时跟踪单元电路的装置和方法。在一个实施例中，一种装置包括一个SRAM阵列，它包括排列成行和列的静态随机存取存储单元; 多条字线，每条字线都沿着一条行与存储器单元耦合; 用于输出时钟信号的时钟发生电路; 字线生成电路，用于响应于所述时钟信号中的一个生成在所述多个字线上的脉冲，并响应于所述时钟信号之一来终止所述脉冲; 以及跟踪单元，用于接收时钟信号并用于在SRAM跟踪时间之后将时钟产生电路输出字线脉冲结束信号; 其中所述跟踪单元还包括位于所述SRAM阵列中并且串联耦合的SRAM跟踪电路，以提供指示所述SRAM跟踪时间的信号。公开了SRAM定时的方法。

26. 发明申请

US20130263066A1 Pre-Colored Methodology of Multiple Patterning 有权
标题翻译：多种图案预色彩方法
公开(公告)号：US20130263066A1
公开(公告)日：2013-10-03
申请号：US13607946
申请日：2012-09-10
申请人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Some embodiments relate to a method of pre-coloring word lines and control lines within an SRAM integrated chip design to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The method is performed by generating a graphical IC layout file having an SRAM circuit with a plurality of word lines and Y-control lines. The word lines and Y-control lines are assigned a color during decomposition. The word lines and Y-control lines are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. Therefore, during mask building, data associated with pre-colored word and Y-control lines is sent to a same mask, regardless of the colors that are assigned to the data. By assigning word and Y-control lines to a same mask through pre-coloring, processing variations between the word and Y-control lines are minimized, thereby mitigating timing variations in an SRAM circuit.
摘要翻译：一些实施例涉及在SRAM集成芯片设计中预先着色字线和控制线的方法，以避免由通过多次图案化光刻工艺引入的处理变化而产生的定时延迟。该方法通过生成具有多个字线和Y控制线的SRAM电路的图形IC布局文件来执行。在分解过程中，字线和Y控制线被分配一个颜色。字线和Y控制线进一步预先着色，以故意将预色数据分配给相同的掩码。因此，在面具构建期间，与预色彩字和Y控制线相关联的数据被发送到相同的掩码，而不管分配给数据的颜色如何。通过预分色将字和Y控制线分配给相同的掩码，字和Y控制线之间的处理变化被最小化，从而减轻SRAM电路中的定时变化。

27. 发明申请

US20120258592A1 Layouts of POLY Cut Openings Overlapping Active Regions 有权
标题翻译： POLY切割开关重叠活动区域的布局
公开(公告)号：US20120258592A1
公开(公告)日：2012-10-11
申请号：US13081115
申请日：2011-04-06
申请人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
发明人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/76816
摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.
摘要翻译：形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

28. 发明申请

US20080158939A1 MEMORY HAVING IMPROVED POWER DESIGN 有权
标题翻译：具有改进功率设计的记忆
公开(公告)号：US20080158939A1
公开(公告)日：2008-07-03
申请号：US11619103
申请日：2007-01-02
申请人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
发明人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.
摘要翻译：存储器包括以具有多个行和多个列的矩阵的形式排列的多个单元，其中每个单元能够存储位。每个单元耦合在接收电源电压的第一电源节点和接收第二电压的第二电源节点之间。多个字线与存储器单元相关联并且在读或写操作中由第三电压提供。第三电压是抑制电源电压。读操作中的第二电压为负，写操作为正。

29. 发明授权

US08455354B2 Layouts of POLY cut openings overlapping active regions 有权
标题翻译： POLY切割开口与活跃区域重叠的布局
公开(公告)号：US08455354B2
公开(公告)日：2013-06-04
申请号：US13081115
申请日：2011-04-06
申请人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
发明人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/76816
摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.
摘要翻译：形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

30. 发明申请

US20100123505A1 ULTRA-LOW VOLTAGE LEVEL SHIFTING CIRCUIT 有权
标题翻译：超低电压电平移位电路
公开(公告)号：US20100123505A1
公开(公告)日：2010-05-20
申请号：US12273365
申请日：2008-11-18
申请人： Shao-Yu Chou , Yen-Huei Chen , Jui-Jen Wu
发明人： Shao-Yu Chou , Yen-Huei Chen , Jui-Jen Wu
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/356182
摘要： A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH.
摘要翻译：公开了一种具有内部低压电源（VCCL）和外部高压电源（VCCH）的集成电路系统的电压电平移动电路，电压电平移位电路包括一对连接到VCCH的交叉耦合PMOS晶体管，具有连接到地（VSS）的源极和连接到在VCCL和VSS之间摆动的第一信号的栅极的NMOS晶体管，以及耦合在第一PMOS晶体管的漏极和第一PMOS晶体管的漏极之间的第一阻断装置 NMOS晶体管，所述第一阻断装置被配置为当所述第一信号处于静态或者从逻辑高电平转换到逻辑低电平时导通有源电流，并且所述第一阻断装置被配置为当所述第一信号从逻辑低电平为逻辑高电平。

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