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21. 发明授权

US5641986A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5641986A
公开(公告)日：1997-06-24
申请号：US587965
申请日：1996-01-17
申请人： Toshiya Uchida
发明人： Toshiya Uchida
IPC分类号： G06F1/26 , G11C5/14 , G11C11/401 , G11C11/407 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/04 , H01L27/108 , H02M3/07 , H01L29/00
CPC分类号： G11C5/14 , G11C5/145 , H01L27/0218
摘要： A semiconductor device includes an increase voltage generation circuit generating an increased voltage having a higher potential than a high potential of a power-supply voltage externally supplied. In the device, an increased voltage stabilizing capacitor is connected between the increased voltage and the high potential of the power-supply voltage, and stabilizes the increased voltage.
摘要翻译：半导体器件包括增加电压产生电路，其产生具有比外部供电的电源电压的高电位更高的电位的增加的电压。在该装置中，增加的稳压电容器连接在增加的电压和电源电压的高电位之间，并且稳定增加的电压。

22. 发明授权

US4865249A Safety device 失效
标题翻译：安全装置
公开(公告)号：US4865249A
公开(公告)日：1989-09-12
申请号：US90746
申请日：1987-08-28
申请人： Mitsutoshi Sugano , Toshiya Uchida , Shigeru Tokita , Atsuhiko Kaneaki , Shigeho Shimada
发明人： Mitsutoshi Sugano , Toshiya Uchida , Shigeru Tokita , Atsuhiko Kaneaki , Shigeho Shimada
IPC分类号： F16K31/70 , F01P11/00 , F01P11/18 , G05D23/02 , G05D23/08 , G05D23/12
CPC分类号： F01P11/18 , G05D23/08 , G05D23/123 , G05D23/1333
摘要： A safety device for an engine cooling system having a heater core circuit for circulating the engine cooling water through the heater core of an automotive air conditioning system, and a radiator circuit for circulating the engine cooling water through a radiator. The safety device comprises a safety valve provided in the heater core circuit and capable of discharging the engine cooling water outside the vehicle when the temperature of the engine cooling water exceeds a predetermined temperature and/or when the pressure of the engine cooling water exceeds a predetermined pressure.
摘要翻译：一种用于发动机冷却系统的安全装置，其具有用于使发动机冷却水循环通过汽车空调系统的加热器芯的加热器核心电路和用于使发动机冷却水循环通过散热器的散热器电路。所述安全装置包括设置在所述加热器芯线路中的安全阀，并且当所述发动机冷却水的温度超过预定温度时，和/或当所述发动机冷却水的压力超过预定温度时，能够将所述发动机冷却水排出到所述车辆外部压力。

23. 发明授权

US08588006B2 Semiconductor memory including switching circuit for selecting data supply 有权
标题翻译：半导体存储器包括用于选择数据提供的切换电路
公开(公告)号：US08588006B2
公开(公告)日：2013-11-19
申请号：US13570158
申请日：2012-08-08
申请人： Hiroyuki Kobayashi , Toshiya Uchida
发明人： Hiroyuki Kobayashi , Toshiya Uchida
IPC分类号： G11C7/10
CPC分类号： G11C11/4096 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C11/4076 , G11C2207/105
摘要： A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.
摘要翻译：提供半导体存储器，其包括：第一焊盘; 邻近所述第一焊盘设置的第二焊盘; 耦合到所述第一焊盘的第一输出缓冲器; 以及耦合到第二焊盘的第二输出缓冲器。第一垫通过金属耦合到第二垫。

24. 发明授权

US08449189B2 Motor with aerodynamic pressure bearing mechanism 有权
标题翻译：电机带气动压力承载机构
公开(公告)号：US08449189B2
公开(公告)日：2013-05-28
申请号：US12451665
申请日：2008-05-21
申请人： Akiyoshi Takahashi , Toshiya Uchida
发明人： Akiyoshi Takahashi , Toshiya Uchida
IPC分类号： F16C32/06
CPC分类号： F16C17/10 , F16C17/026 , F16C17/045 , F16C33/1015
摘要： In a gas dynamic pressure bearing mechanism (1) for smoothing rotary motion of a shaft (10) by feeding gas to the bearing clearance between the shaft (10) and a fixed sleeve (20) for supporting the shaft (10) through a herring bone groove (10a), the herring bone groove (10a) is provided in the shaft (10) such that pressure distribution generated in the bearing clearance moves at a high speed. The herring bone groove (10a) consists of N grooves such that N minimal pressure values appearing alternately with maximal pressure values at the positions where the maximal pressure values of dynamic pressure variation appear in the bearing clearance when the shaft (10) rotates have such an interval as it becomes lower than the condensation pressure value.
摘要翻译：在用于通过将气体输送到轴（10）和用于通过鲱鱼支撑轴（10）的固定套筒（20）之间的轴承间隙的方法来平滑轴（10）的旋转运动的气体动压轴承机构（1）骨槽（10a），在轴（10）中设置有珩骨槽（10a），使得在轴承间隙中产生的压力分布高速移动。鲱鱼骨槽（10a）由N个沟槽组成，使得当轴（10）旋转时在轴承间隙中出现动态压力变化的最大压力值的位置处交替具有最大压力值的N个最小压力值具有这样的间隔，因为它变得低于冷凝压力值。

25. 发明申请

US20080151677A1 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US20080151677A1
公开(公告)日：2008-06-26
申请号：US11698286
申请日：2007-01-26
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C8/12
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译：提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中，在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

26. 发明申请

US20080104458A1 Semiconductor memory, system, testing method for system 审中-公开
标题翻译：半导体存储器，系统，系统测试方法
公开(公告)号：US20080104458A1
公开(公告)日：2008-05-01
申请号：US11907996
申请日：2007-10-19
申请人： Toshiya Uchida
发明人： Toshiya Uchida
IPC分类号： G06F11/277
CPC分类号： G11C29/36 , G11C2029/0401 , G11C2029/3602
摘要： A plurality of test patterns generated by a test pattern generator is output from a first memory chip to test a second memory chip, which is of a different type from the first memory chip and mounted in the same package. Therefore, when different types of memory chips are mounted in the same package, the memory chip is tested even no terminal of the memory chip is connected to an external terminal of a system. Since there is no need to form any useless terminal in the system, system cost is reduced. Since a testing apparatus generating complicated test patterns is made unnecessary, test cost is reduced. The test pattern generator is constructed using nonvolatile logic and therefore, tests can be carried out without preparing test patterns in advance. Consequently, a user who purchases the first and second memory chips to construct a system can also carry out tests easily.
摘要翻译：从第一存储器芯片输出由测试图形发生器产生的多个测试图案，以测试与第一存储器芯片不同类型并安装在相同封装中的第二存储器芯片。因此，当不同类型的存储器芯片安装在相同的封装中时，即使没有存储器芯片的端子连接到系统的外部端子，也对存储器芯片进行测试。由于不需要在系统中形成无用的终端，所以系统成本降低。由于不需要产生复杂的测试图案的测试装置，所以测试成本降低。使用非易失性逻辑构造测试图形生成器，因此可以在不预先准备测试图案的情况下进行测试。因此，购买第一和第二存储器芯片以构建系统的用户也可以容易地进行测试。

27. 发明申请

US20060092752A1 Multiple chip package and IC chips 有权
标题翻译：多芯片封装和IC芯片
公开(公告)号：US20060092752A1
公开(公告)日：2006-05-04
申请号：US11043993
申请日：2005-01-28
申请人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
发明人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/49113 , H01L2924/3011 , H01L2924/00
摘要： A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.
摘要翻译：时钟输出板和返回时钟接收焊盘设置在集成电路芯片的靠近侧面的部分和与集成电路芯片的与侧面相反的另一侧的部分的逻辑芯片上。时钟接收垫分别在靠近侧面和另一侧的部分设置在存储器芯片上。时钟接收板电连接到时钟输出板和返回时钟接收板。多个时钟信号从逻辑芯片提供给存储器芯片，并且多个返回时钟信号从存储器芯片返回到逻辑芯片。

28. 发明授权

US06999358B2 Semiconductor memory device 失效
公开(公告)号：US06999358B2
公开(公告)日：2006-02-14
申请号：US10671473
申请日：2003-09-29
申请人： Yoshimasa Yagishita , Toshiya Uchida
发明人： Yoshimasa Yagishita , Toshiya Uchida
IPC分类号： G11C7/00 , G11C7/02 , G11C8/00 , G11C5/06
CPC分类号： G11C29/80 , G11C29/848
摘要： A semiconductor memory device that reduces the probability of the penalties of wirings arising. An address input circuit receives an address signal input. A drive circuit drives a memory array in compliance with the address signal. A signal line connects the address input circuit and the drive circuit. A redundant circuit is located near the drive circuit and substitutes other lines including a redundant line for a defective line in the memory array. A defective line information store circuit stores information showing the defective line. A supply circuit supplies information stored in the defective line information store circuit to the redundant circuit via the signal line. This structure enables to transmit an address signal and information regarding a defective line by a common signal line and to reduce the number of wirings and the probability of the penalties of wirings arising.

29. 发明授权

US06876225B2 Input/output interfacing circuit, input/output interface, and semiconductor device having input/out interfacing circuit 失效
标题翻译：输入/输出接口电路，输入/输出接口和具有输入/输出接口电路的半导体器件
公开(公告)号：US06876225B2
公开(公告)日：2005-04-05
申请号：US10178559
申请日：2002-06-25
申请人： Yoshimasa Yagishita , Toshiya Uchida
发明人： Yoshimasa Yagishita , Toshiya Uchida
IPC分类号： G06F3/00 , H03K19/00 , H03K19/0175 , H03K19/20 , H03K17/16
CPC分类号： H03K19/0002 , H03K19/017509
摘要： The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents with output current from the transmitter and restores the logic values. That is, the current is varied in correspondence with the logic values that are transmitted from the transmitter to the receiver, wherein the logic values are restored in the receiver according to a difference in the current value. Forming a plurality of current comparing units in the receiver makes it possible to easily compare the values of the output current from the transmitter and a plurality of reference currents. Therefore, the number of multi-valued bits can be easily increased so as to construct a high bit-rate multi-valued input/output interface.
摘要翻译：发射机中的电流产生单元根据多个逻辑值产生输出电流。接收器中的参考电流产生单元产生多个参考电流。接收器中的当前比较单元分别将参考电流与来自发射器的输出电流进行比较，并恢复逻辑值。也就是说，电流根据从发射机发送到接收机的逻辑值而变化，其中根据当前值的差异在接收机中恢复逻辑值。在接收机中形成多个电流比较单元使得可以容易地比较来自发射器的输出电流和多个参考电流的值。因此，可以容易地增加多值比特的数量，以便构成高比特率多值输入/输出接口。

30. 发明授权

US06696859B2 Input/output interfacing circuit, input/output interface, and semiconductor device having input/out interfacing circuit 有权
标题翻译：输入/输出接口电路，输入/输出接口和具有输入/输出接口电路的半导体器件
公开(公告)号：US06696859B2
公开(公告)日：2004-02-24
申请号：US10178519
申请日：2002-06-25
申请人： Yoshimasa Yagishita , Toshiya Uchida
发明人： Yoshimasa Yagishita , Toshiya Uchida
IPC分类号： H03K190175
CPC分类号： H03K19/0002 , H03K19/017509
摘要： The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents with output current from the transmitter and restores the logic values. That is, the current is varied in correspondence with the logic values that are transmitted from the transmitter to the receiver, wherein the logic values are restored in the receiver according to a difference in the current value. Forming a plurality of current comparing units in the receiver makes it possible to easily compare the values of the output current from the transmitter and a plurality of reference currents. Therefore, the number of multi-valued bits can be easily increased so as to construct a high bit-rate multi-valued input/output interface.
摘要翻译：发射机中的电流产生单元根据多个逻辑值产生输出电流。接收器中的参考电流产生单元产生多个参考电流。接收器中的当前比较单元分别将参考电流与来自发射器的输出电流进行比较，并恢复逻辑值。也就是说，电流根据从发射机发送到接收机的逻辑值而变化，其中根据当前值的差异在接收机中恢复逻辑值。在接收机中形成多个电流比较单元使得可以容易地比较来自发射器的输出电流和多个参考电流的值。因此，可以容易地增加多值比特的数量，以便构成高比特率多值输入/输出接口。

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