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21. 发明授权

US06333265B1 Low pressure, low temperature, semiconductor gap filling process 失效
标题翻译：低压，低温，半导体缺口填充工艺
公开(公告)号：US06333265B1
公开(公告)日：2001-12-25
申请号：US08766199
申请日：1996-12-12
申请人： Girish A. Dixit , Anthony Konecni , Robert H. Havemann
发明人： Girish A. Dixit , Anthony Konecni , Robert H. Havemann
IPC分类号： H01L2144
CPC分类号： H01L21/76882 , H01L21/76838 , H01L21/76843 , H01L21/76862
摘要： A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;
摘要翻译：提供了用于填充诸如触点和通孔的集成电路腔的结构和工艺。这些结构在不超过约300℃，优选在约20°-275℃之间的较低温度下填充，该温度范围允许使用低介电常数（κ）聚合物（即，〜3.0）。优选地，空腔设置有不含钛的衬垫以促进空腔填充，并且空腔填充有CVD铝，其通过在大气压至约50MPa的压力下的强力填充物引入空腔中，并且优选地在约100°-300℃的温度下不超过约30Mpa。以上述方式填充的空腔表现出比通过常规实践填充的结构小至多30％的电阻水平。

22. 发明授权

US06268297B1 Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces 有权
标题翻译：自平坦化低温掺杂硅酸盐玻璃工艺，能够填补狭窄的空间
公开(公告)号：US06268297B1
公开(公告)日：2001-07-31
申请号：US09196725
申请日：1998-11-20
申请人： Somnath S. Nag , Gregory B. Shinn , Girish A. Dixit
发明人： Somnath S. Nag , Gregory B. Shinn , Girish A. Dixit
IPC分类号： H01L21469
CPC分类号： H01L21/02304 , H01L21/02129 , H01L21/02274 , H01L21/31051 , H01L21/31604 , H01L21/31625 , H01L21/76801
摘要： A low-temperature pre-metal dielectric deposition process using phosphine-based chemistry in a high-density plasma chemical-vapor deposition technique. The process uses a phosphorous-doped oxide of up to 3.5 percent (wt) deposited at less than 350 degrees C. capable of filling 0.4 micron spaces between poly-silicon gates without microvoids.
摘要翻译：在高密度等离子体化学气相沉积技术中使用基于膦的化学的低温预金属介电沉积方法。该方法使用在低于350℃下沉积的高达3.5％（重量）的磷掺杂氧化物，能够在没有微孔的多晶硅栅极之间填充0.4微米的空间。

23. 发明授权

US06159847A Multilayer metal structure for improved interconnect reliability 有权
标题翻译：多层金属结构，提高互连可靠性
公开(公告)号：US06159847A
公开(公告)日：2000-12-12
申请号：US191027
申请日：1998-11-12
申请人： Robert H. Havemann , Girish A. Dixit
发明人： Robert H. Havemann , Girish A. Dixit
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L21/7685 , H01L21/76843 , H01L21/76877 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： AlCu alloys with higher Cu content are added in thin layers within a metallization structure. The increased Cu content provided by the thin layer improves interconnect reliability and reduces the effects of electromigration with minimal effect on plasma etch and cleanup processes.
摘要翻译：具有较高Cu含量的AlCu合金以金属化结构内的薄层加入。由薄层提供的增加的Cu含量提高了互连可靠性，并且减少电迁移的影响，对等离子体蚀刻和清除过程的影响最小。

24. 发明授权

US5849367A Elemental titanium-free liner and fabrication process for inter-metal connections 失效
标题翻译：元素无钛衬里和金属间连接的制造工艺
公开(公告)号：US5849367A
公开(公告)日：1998-12-15
申请号：US764674
申请日：1996-12-11
申请人： Girish A. Dixit , Anthony J. Konecni
发明人： Girish A. Dixit , Anthony J. Konecni
IPC分类号： C23C14/02 , H01L21/768
CPC分类号： H01L21/76846 , C23C14/022 , H01L21/76814 , H01L21/76843 , H01L21/76862 , H01L21/76877
摘要： An elemental titanium-free liner and cavity cleansing process is provided that allows for the elimination of conventional sputter etch and elemental titanium depositions. A low power plasma etch provides for pre-conditioning/cleansing of cavities such as contacts and vias. A refractory metal is provided as a cavity liner. Preferably, the liner is comprised of several discrete refractory metal liner layers, each having a thickness of about 25-100 .ANG., that can be applied by CVD and/or PVD. A low power plasma cleanse is preferably interposed between each liner layer deposition. A suitable metal plug can be deposited and directed into the cavity to complete cavity filling. Preferably, the metal plug is an elemental aluminum or aluminum alloy plug that is deposited by CVD and force-filled into the cavity to reduce the incidence of micro-voids within the cavity. Elimination of the conventional sputter etch and the high temperature processing (temp..gtoreq..sup..about. 400.degree. C.) associated with such processing allows for the use of polymeric dielectrics, such as the family of polytetrafluorethylene ("PTFE") compounds, which exhibit a dielectric constant (.kappa.) of about 1.9; parylene (.kappa.=.sup..about. 2.2-2.6); aerogels and xerogels (.kappa.=.sup..about. 1.1-1.8); and the family of polymeric spin-on-glass ("SOG") materials; use of all the foregoing materials being attractive because of the ability of these materials to reduce parasitic capacitance of the interconnects. Because these polymeric materials are temperature sensitive, their use has been limited, as conventional device fabrication practices typically require operation temperatures far in excess of the melting and/or decomposition temperature for these materials.
摘要翻译：提供了元素无钛衬里和空腔清洁工艺，其允许消除常规的溅射蚀刻和元素钛沉积。低功率等离子体蚀刻提供诸如触点和通孔之类的空腔的预调节/清洁。提供难熔金属作为空腔衬垫。优选地，衬套由几个分立的难熔金属衬垫层组成，每层具有约25-100的厚度，可以通过CVD和/或PVD施加。优选地，在每个衬垫层沉积之间插入低功率等离子体清洁。可以将合适的金属塞子沉积并引导到空腔中以完成空腔填充。优选地，金属插塞是元素铝或铝合金插塞，其通过CVD沉积并强力填充到空腔中以减少空腔内的微孔的入射。消除常规的溅射蚀刻和与这种处理相关的高温处理（温度> = = DIFFERENCE 400℃）允许使用聚合物电介质，例如聚四氟乙烯（“PTFE”）族化合物，其表现出介电常数（kappa）约为1.9; 聚对二甲苯（kappa = DIFFERENCE 2.2-2.6）; 气凝胶和干凝胶（kappa = DIFFERENCE 1.1-1.8）; 和聚合物旋涂玻璃（“SOG”）材料的家族; 使用所有上述材料是有吸引力的，因为这些材料能够减少互连的寄生电容。由于这些聚合物材料是温度敏感的，因此其使用受到限制，因为传统的器件制造实践通常需要远远超过这些材料的熔化和/或分解温度的操作温度。

25. 发明授权

US5847457A Structure and method of forming vias 失效
标题翻译：形成通孔的结构和方法
公开(公告)号：US5847457A
公开(公告)日：1998-12-08
申请号：US738040
申请日：1996-10-24
申请人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
发明人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
IPC分类号： H01L23/522 , H01L23/48
CPC分类号： H01L23/5226 , H01L2924/0002
摘要： A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.
摘要翻译：提供一种用于形成半导体集成电路的接触开口或通路的方法，以及根据该集成电路形成的集成电路。在下面的区域上形成第一金属区域。在集成电路上形成第一绝缘层。然后在第一绝缘层上形成第二绝缘层。蚀刻第二绝缘层的一部分以暴露第一绝缘层的一部分，其中暴露的第一绝缘层和剩余的第二绝缘层形成基本平坦的表面。在暴露的第一绝缘层和剩余的第二绝缘层上形成金属氧化物层。在金属氧化物层上形成并图案化光致抗蚀剂层。然后选择性地蚀刻金属氧化物层以形成露出第一绝缘层的一部分的通孔。然后选择性地蚀刻通孔中的第一绝缘层以暴露第一金属区域的一部分。去除光致抗蚀剂层，然后在金属氧化物层上形成第二金属层，并在通孔中与第一金属区接触。

26. 发明授权

US5593921A Method of forming vias 失效
标题翻译：形成通孔的方法
公开(公告)号：US5593921A
公开(公告)日：1997-01-14
申请号：US438167
申请日：1995-05-09
申请人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
发明人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
IPC分类号： H01L21/768 , H01L23/522 , H01L21/441
CPC分类号： H01L21/76802 , Y10S148/043 , Y10S148/118
摘要： A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.
摘要翻译：提供一种用于形成半导体集成电路的接触开口或通路的方法，以及根据该集成电路形成的集成电路。在下面的区域上形成第一金属区域。在集成电路上形成第一绝缘层。然后在第一绝缘层上形成第二绝缘层。蚀刻第二绝缘层的一部分以暴露第一绝缘层的一部分，其中暴露的第一绝缘层和剩余的第二绝缘层形成基本平坦的表面。在暴露的第一绝缘层和剩余的第二绝缘层上形成金属氧化物层。在金属氧化物层上形成并图案化光致抗蚀剂层。然后选择性地蚀刻金属氧化物层以形成露出第一绝缘层的一部分的通孔。然后选择性地蚀刻通孔中的第一绝缘层以暴露第一金属区域的一部分。去除光致抗蚀剂层，然后在金属氧化物层上形成第二金属层，并在通孔中与第一金属区接触。

27. 发明授权

US5521411A Transistor spacer etch pinpoint structure 失效
标题翻译：晶体管间隔蚀刻精确点结构
公开(公告)号：US5521411A
公开(公告)日：1996-05-28
申请号：US271565
申请日：1994-07-07
申请人： Fusen E. Chen , Frank R. Bryant , Girish A. Dixit
发明人： Fusen E. Chen , Frank R. Bryant , Girish A. Dixit
IPC分类号： H01L21/266 , H01L21/336 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6659 , H01L21/266 , H01L29/6656
摘要： A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a substrate. A dielectric layer is formed over the integrated circuit and an oxide layer is formed over the dielectric layer. the oxide layer is patterned and etched to form sidewall oxide spacers on each side of the gate and over a portion of the dielectric layer. The dielectric layer not covered by the sidewall oxide spacers is then removed.
摘要翻译：提供一种用于形成集成电路的晶体管间隔物蚀刻端点结构的方法，以及根据该集成电路形成的集成电路。栅极形成在衬底的一部分上。在集成电路上形成电介质层，并且在电介质层上形成氧化物层。对氧化物层进行图案化和蚀刻以在栅极的每一侧和电介质层的一部分上形成侧壁氧化物间隔物。然后除去未被侧壁氧化物间隔物覆盖的电介质层。

28. 发明授权

US5348901A Interconnect and resistor for integrated circuits 失效
标题翻译：集成电路的互连和电阻
公开(公告)号：US5348901A
公开(公告)日：1994-09-20
申请号：US911167
申请日：1992-07-09
申请人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
发明人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
IPC分类号： H01L21/265 , H01L21/02 , H01L21/316 , H01L21/768 , H01L23/522 , H01L27/00 , H01L27/10 , H01L27/11 , H01L21/205 , H01L21/285
CPC分类号： H01L28/20 , H01L21/76889 , H01L27/1112
摘要： A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.
摘要翻译：提供一种用于形成半导体集成电路的多晶硅电阻性负载元件的方法和根据该集成电路形成的集成电路。具有第一类型的导电性的轻掺杂的第一导电层。在集成电路上形成第一氧化物层，其中第一开口穿过其暴露第一导电层的一部分。使用第一氧化物层作为掩模，然后用第二导电类型的掺杂剂注入第一导电层的暴露部分，以形成暴露部分和被掩模覆盖的部分之间的结。然后在第一开口中的第一氧化物层的一部分上形成第二氧化物区域，并且在接合处以及暴露的第一导电层的与接合部相邻的部分上形成第二氧化物区域。在第一导电层的暴露部分上形成硅化物。

29. 发明授权

US5278098A Method for self-aligned polysilicon contact formation 失效
标题翻译：自对准多晶硅接触形成方法
公开(公告)号：US5278098A
公开(公告)日：1994-01-11
申请号：US939951
申请日：1992-09-03
申请人： Che C. Wei , Chiara Zaccherini , Robert O. Miller , Girish A. Dixit
发明人： Che C. Wei , Chiara Zaccherini , Robert O. Miller , Girish A. Dixit
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/74 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/88 , H01L21/316 , H01L21/78
CPC分类号： H01L21/76889 , H01L21/28525 , H01L21/76895 , H01L21/76897 , H01L23/53271 , H01L2924/0002
摘要： A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact openings to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.
摘要翻译：沉积并图案化多晶硅层以限定互连水平。然后对下导电层的接触开口进行限定和图案化。诸如钨的难熔金属被选择性地沉积在器件上，使得其粘附到互连引线中的多晶硅和暴露在接触开口中的下导电层的硅。这提供了低电阻互连，以及良好的金属触点到底层。使用该技术容易地形成两个或更多个多晶硅互连层之间和底层导电层（例如基板）中的共用接触。

30. 发明授权

US07115534B2 Dielectric materials to prevent photoresist poisoning 失效
标题翻译：介电材料防止光致抗蚀剂中毒
公开(公告)号：US07115534B2
公开(公告)日：2006-10-03
申请号：US10847891
申请日：2004-05-18
申请人： Son Van Nguyen , Michael D. Armacost , Mehul Naik , Girish A. Dixit , Ellie Y. Yieh
发明人： Son Van Nguyen , Michael D. Armacost , Mehul Naik , Girish A. Dixit , Ellie Y. Yieh
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76808
摘要： Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.
摘要翻译：提供了用于沉积电介质材料的方法，用作防蚀涂层和牺牲电介质材料在镶嵌形成中。在一个方面，提供了一种处理衬底的方法，包括通过使含氧有机硅化合物和酸性化合物反应，在酸性电介质层上沉积光致抗蚀剂材料，并使光致抗蚀剂层图形化，在衬底上沉积酸性介电层。通过蚀刻部分特征定义，沉积酸性电介质材料，蚀刻特征定义的其余部分，然后除去酸性介电材料以形成特征定义，可以将酸性介电层用作形成特征定义的牺牲层。

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