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1. 发明授权

US5847457A Structure and method of forming vias 失效
标题翻译：形成通孔的结构和方法
公开(公告)号：US5847457A
公开(公告)日：1998-12-08
申请号：US738040
申请日：1996-10-24
申请人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
发明人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
IPC分类号： H01L23/522 , H01L23/48
CPC分类号： H01L23/5226 , H01L2924/0002
摘要： A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.
摘要翻译：提供一种用于形成半导体集成电路的接触开口或通路的方法，以及根据该集成电路形成的集成电路。在下面的区域上形成第一金属区域。在集成电路上形成第一绝缘层。然后在第一绝缘层上形成第二绝缘层。蚀刻第二绝缘层的一部分以暴露第一绝缘层的一部分，其中暴露的第一绝缘层和剩余的第二绝缘层形成基本平坦的表面。在暴露的第一绝缘层和剩余的第二绝缘层上形成金属氧化物层。在金属氧化物层上形成并图案化光致抗蚀剂层。然后选择性地蚀刻金属氧化物层以形成露出第一绝缘层的一部分的通孔。然后选择性地蚀刻通孔中的第一绝缘层以暴露第一金属区域的一部分。去除光致抗蚀剂层，然后在金属氧化物层上形成第二金属层，并在通孔中与第一金属区接触。

2. 发明授权

US5593921A Method of forming vias 失效
标题翻译：形成通孔的方法
公开(公告)号：US5593921A
公开(公告)日：1997-01-14
申请号：US438167
申请日：1995-05-09
申请人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
发明人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit
IPC分类号： H01L21/768 , H01L23/522 , H01L21/441
CPC分类号： H01L21/76802 , Y10S148/043 , Y10S148/118
摘要： A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.
摘要翻译：提供一种用于形成半导体集成电路的接触开口或通路的方法，以及根据该集成电路形成的集成电路。在下面的区域上形成第一金属区域。在集成电路上形成第一绝缘层。然后在第一绝缘层上形成第二绝缘层。蚀刻第二绝缘层的一部分以暴露第一绝缘层的一部分，其中暴露的第一绝缘层和剩余的第二绝缘层形成基本平坦的表面。在暴露的第一绝缘层和剩余的第二绝缘层上形成金属氧化物层。在金属氧化物层上形成并图案化光致抗蚀剂层。然后选择性地蚀刻金属氧化物层以形成露出第一绝缘层的一部分的通孔。然后选择性地蚀刻通孔中的第一绝缘层以暴露第一金属区域的一部分。去除光致抗蚀剂层，然后在金属氧化物层上形成第二金属层，并在通孔中与第一金属区接触。

3. 发明授权

US5930673A Method for forming a metal contact 失效
标题翻译：形成金属接触的方法
公开(公告)号：US5930673A
公开(公告)日：1999-07-27
申请号：US418122
申请日：1995-04-06
申请人： Fusen E. Chen , Fu-Tai Liou , Yih-Shung Lin , Girish A. Dixit , Che-Chia Wei
发明人： Fusen E. Chen , Fu-Tai Liou , Yih-Shung Lin , Girish A. Dixit , Che-Chia Wei
IPC分类号： H01L21/28 , C23C16/02 , C23C16/20 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/283
CPC分类号： H01L21/76843 , C23C16/0281 , C23C16/20 , H01L21/28512 , H01L21/32051 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L2924/0002
摘要： A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.
摘要翻译：提供了一种用于在半导体集成电路器件中沉积铝薄膜层以形成接触的方法。所有或一些沉积过程在允许改善沉积的铝原子的表面迁移的温度下以相对较低的沉积速率进行。在这些条件下沉积的铝倾向于填充接触孔而不形成空隙。低温沉积步骤可以通过沉积铝来开始，而包含集成电路器件的晶片正在从沉积室内的较冷的温度加热。

4. 发明授权

US5108951A Method for forming a metal contact 失效
标题翻译：形成金属接触的方法
公开(公告)号：US5108951A
公开(公告)日：1992-04-28
申请号：US609883
申请日：1990-11-05
申请人： Fusen E. Chen , Fu-Tai Liou , Yih-Shung Lin , Girish A. Dixit , Che-Chia Wei
发明人： Fusen E. Chen , Fu-Tai Liou , Yih-Shung Lin , Girish A. Dixit , Che-Chia Wei
IPC分类号： H01L21/28 , C23C16/02 , C23C16/20 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/485 , H01L23/532
CPC分类号： H01L21/76843 , C23C16/0281 , C23C16/20 , H01L21/28512 , H01L21/32051 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L2924/0002
摘要： A method is provided for depositing aluminum thin film layers to form improved quality contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

5. 发明授权

US06287963B1 Method for forming a metal contact 失效
标题翻译：形成金属接触的方法
公开(公告)号：US06287963B1
公开(公告)日：2001-09-11
申请号：US08418257
申请日：1995-04-06
申请人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit , Che-Chia Wei
发明人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit , Che-Chia Wei
IPC分类号： H01L214763
CPC分类号： H01L23/53223 , C23C16/0281 , C23C16/20 , H01L21/28512 , H01L21/32051 , H01L21/7684 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The deposition step is periodically interrupted.
摘要翻译：提供了一种用于在半导体集成电路器件中沉积铝薄膜层以形成接触的方法。所有或一些沉积过程在允许沉积的铝原子的表面迁移的温度下以相对低的沉积速率发生。在这些条件下沉积的铝倾向于填充接触孔而不形成空隙。沉积步骤被周期性地中断。

6. 发明授权

US5075761A Local interconnect for integrated circuits 失效
标题翻译：集成电路的局部互连
公开(公告)号：US5075761A
公开(公告)日：1991-12-24
申请号：US567270
申请日：1990-08-14
申请人： Fu-Tai Liou , Yih-Shung Lin , Fusen E. Chen
发明人： Fu-Tai Liou , Yih-Shung Lin , Fusen E. Chen
IPC分类号： H01L21/285 , H01L21/3215 , H01L21/336 , H01L21/768 , H01L23/532
CPC分类号： H01L29/6659 , H01L21/28518 , H01L21/32155 , H01L21/76895 , H01L23/53271 , H01L2924/0002
摘要： A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.
摘要翻译：在第一层多晶硅上形成硅化物层，以提高导电性，随后是第二层多晶硅。然后将该结构图案化以在有效区域上形成栅极区域。在芯片的整个表面上形成金属硅化物层，并且被图案化以形成局部互连。通过第二多晶硅层阻止第二金属硅化物层的蚀刻，从而保护第一金属硅化物层免受损坏。

7. 发明授权

US5521411A Transistor spacer etch pinpoint structure 失效
标题翻译：晶体管间隔蚀刻精确点结构
公开(公告)号：US5521411A
公开(公告)日：1996-05-28
申请号：US271565
申请日：1994-07-07
申请人： Fusen E. Chen , Frank R. Bryant , Girish A. Dixit
发明人： Fusen E. Chen , Frank R. Bryant , Girish A. Dixit
IPC分类号： H01L21/266 , H01L21/336 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6659 , H01L21/266 , H01L29/6656
摘要： A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a substrate. A dielectric layer is formed over the integrated circuit and an oxide layer is formed over the dielectric layer. the oxide layer is patterned and etched to form sidewall oxide spacers on each side of the gate and over a portion of the dielectric layer. The dielectric layer not covered by the sidewall oxide spacers is then removed.
摘要翻译：提供一种用于形成集成电路的晶体管间隔物蚀刻端点结构的方法，以及根据该集成电路形成的集成电路。栅极形成在衬底的一部分上。在集成电路上形成电介质层，并且在电介质层上形成氧化物层。对氧化物层进行图案化和蚀刻以在栅极的每一侧和电介质层的一部分上形成侧壁氧化物间隔物。然后除去未被侧壁氧化物间隔物覆盖的电介质层。

8. 发明授权

US5348901A Interconnect and resistor for integrated circuits 失效
标题翻译：集成电路的互连和电阻
公开(公告)号：US5348901A
公开(公告)日：1994-09-20
申请号：US911167
申请日：1992-07-09
申请人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
发明人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
IPC分类号： H01L21/265 , H01L21/02 , H01L21/316 , H01L21/768 , H01L23/522 , H01L27/00 , H01L27/10 , H01L27/11 , H01L21/205 , H01L21/285
CPC分类号： H01L28/20 , H01L21/76889 , H01L27/1112
摘要： A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.
摘要翻译：提供一种用于形成半导体集成电路的多晶硅电阻性负载元件的方法和根据该集成电路形成的集成电路。具有第一类型的导电性的轻掺杂的第一导电层。在集成电路上形成第一氧化物层，其中第一开口穿过其暴露第一导电层的一部分。使用第一氧化物层作为掩模，然后用第二导电类型的掺杂剂注入第一导电层的暴露部分，以形成暴露部分和被掩模覆盖的部分之间的结。然后在第一开口中的第一氧化物层的一部分上形成第二氧化物区域，并且在接合处以及暴露的第一导电层的与接合部相邻的部分上形成第二氧化物区域。在第一导电层的暴露部分上形成硅化物。

9. 发明授权

US5146309A Method for forming polycrystalline silicon contacts 失效
标题翻译：多晶硅触点形成方法
公开(公告)号：US5146309A
公开(公告)日：1992-09-08
申请号：US705775
申请日：1991-05-28
申请人： Charles R. Spinner , Fusen E. Chen , Fu-Tai Liou
发明人： Charles R. Spinner , Fusen E. Chen , Fu-Tai Liou
IPC分类号： H01L21/285
CPC分类号： H01L21/28525
摘要： A method for fabricating integrated circuits is used to improve contacts between polycrystalline interconnect and underlying polycrystalline or monocrystalline silicon regions. After contact openings are formed, a layer of titanium is deposited over the integrated circuit. The titanium is reacted in nitrogen to form a silicide layer only in the openings. Titanium nitride and unreacted titanium are then removed, and a layer of polycrystalline silicon deposited and patterned. The silicide layer between the polycrystalline interconnect and the underlying silicon ensures that a high quality contact is formed.
摘要翻译：用于制造集成电路的方法用于改善多晶互连和下面的多晶或单晶硅区域之间的接触。在形成接触开口之后，在集成电路上沉积一层钛。钛在氮中反应，仅在开口中形成硅化物层。然后去除氮化钛和未反应的钛，并沉积并图案化一层多晶硅。多晶互连和底层硅之间的硅化物层确保形成高质量的接触。

10. 发明授权

US4978637A Local interconnect process for integrated circuits 失效
标题翻译：集成电路的局部互连过程
公开(公告)号：US4978637A
公开(公告)日：1990-12-18
申请号：US359860
申请日：1989-05-31
申请人： Fu-Tai Liou , Yih-Shung Lin , Fusen E. Chen
发明人： Fu-Tai Liou , Yih-Shung Lin , Fusen E. Chen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3215 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L23/532 , H01L27/06 , H01L27/088 , H01L27/092 , H01L27/10 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28518 , H01L21/32155 , H01L21/76895 , H01L23/53271 , H01L29/78 , H01L2924/0002 , Y10S148/015 , Y10S148/019 , Y10S148/02
摘要： A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.
摘要翻译：在第一层多晶硅上形成硅化物层，以提高导电性，随后是第二层多晶硅。然后将该结构图案化以在有效区域上形成栅极区域。在芯片的整个表面上形成金属硅化物层，并且被图案化以形成局部互连。通过第二多晶硅层阻止第二金属硅化物层的蚀刻，从而保护第一金属硅化物层免受损坏。

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