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1. 发明授权

US5491355A Self-aligned contact formation 失效
标题翻译：自对准接触形成
公开(公告)号：US5491355A
公开(公告)日：1996-02-13
申请号：US97366
申请日：1993-07-23
申请人： Che C. Wei , Chiara Zaccherini , Robert O. Miller , Girish A. Dixit
发明人： Che C. Wei , Chiara Zaccherini , Robert O. Miller , Girish A. Dixit
IPC分类号： H01L21/74 , H01L21/768 , H01L23/485 , H01L29/45 , H01L29/04
CPC分类号： H01L21/76895 , H01L21/743 , H01L23/485 , H01L29/456 , H01L2924/0002
摘要： A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact opening to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.
摘要翻译：沉积并图案化多晶硅层以限定互连水平。然后对下导电层的接触开口被限定和图案化。诸如钨的难熔金属被选择性地沉积在器件上，使得其粘附到互连引线中的多晶硅和暴露在接触开口中的下导电层的硅。这提供了低电阻互连，以及良好的金属触点到底层。使用该技术容易地形成两个或更多个多晶硅互连层之间和底层导电层（例如基板）中的共用接触。

2. 发明授权

US5278098A Method for self-aligned polysilicon contact formation 失效
标题翻译：自对准多晶硅接触形成方法
公开(公告)号：US5278098A
公开(公告)日：1994-01-11
申请号：US939951
申请日：1992-09-03
申请人： Che C. Wei , Chiara Zaccherini , Robert O. Miller , Girish A. Dixit
发明人： Che C. Wei , Chiara Zaccherini , Robert O. Miller , Girish A. Dixit
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/74 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/88 , H01L21/316 , H01L21/78
CPC分类号： H01L21/76889 , H01L21/28525 , H01L21/76895 , H01L21/76897 , H01L23/53271 , H01L2924/0002
摘要： A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact openings to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.
摘要翻译：沉积并图案化多晶硅层以限定互连水平。然后对下导电层的接触开口进行限定和图案化。诸如钨的难熔金属被选择性地沉积在器件上，使得其粘附到互连引线中的多晶硅和暴露在接触开口中的下导电层的硅。这提供了低电阻互连，以及良好的金属触点到底层。使用该技术容易地形成两个或更多个多晶硅互连层之间和底层导电层（例如基板）中的共用接触。

3. 发明授权

US5578872A Planar contact with a void 失效
标题翻译：与空虚平面接触
公开(公告)号：US5578872A
公开(公告)日：1996-11-26
申请号：US418838
申请日：1995-04-07
申请人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
发明人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L29/41 , H01L29/43
CPC分类号： H01L21/76843 , H01L21/76877 , Y10S257/915
摘要： A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.
摘要翻译：提供了用于图案化集成电路的亚微米半导体层的方法，以及根据该集成电路形成的集成电路。在集成电路上形成第一导电结构。在第一导电结构上形成电介质，其具有暴露下面的第一导电层的一部分的接触开口。阻挡层形成在接触开口的底部。通过化学气相沉积在介电层上形成第二基本上保形的导电层; 沿着接触开口的侧壁和底部。然后在第二导电层上形成第三导电层，其中第三导电层不填充接触开口。第二和第三导电层被蚀刻以形成基本上在接触开口上的互连。

4. 发明授权

US5523624A Integrated circuit device structure with dielectric and metal stacked plug in contact hole 失效
标题翻译：集成电路器件结构，电介质和金属堆叠插头接触孔
公开(公告)号：US5523624A
公开(公告)日：1996-06-04
申请号：US112863
申请日：1993-08-26
申请人： Fusen E. Chen , Robert O. Miller , Girish A. Dixit
发明人： Fusen E. Chen , Robert O. Miller , Girish A. Dixit
IPC分类号： H01L21/28 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L29/417 , H01L29/43
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/76843 , H01L21/76844 , H01L21/76877 , Y10S257/915
摘要： A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.
摘要翻译：提供了用于图案化集成电路的亚微米半导体层的方法，以及根据该集成电路形成的集成电路。在集成电路上形成导体结构。在集成电路上形成介电层。在电介质层中形成接触开口，暴露下面的第一导电结构的一部分。在电介质层和接触开口中形成阻挡层。在阻挡层和接触开口中形成基本上共形的层。共形层被部分蚀刻掉，其中保形层仅保留在接触开口的底部。在阻挡层和剩余的保形层上形成第二导电层。

5. 发明授权

US5348901A Interconnect and resistor for integrated circuits 失效
标题翻译：集成电路的互连和电阻
公开(公告)号：US5348901A
公开(公告)日：1994-09-20
申请号：US911167
申请日：1992-07-09
申请人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
发明人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
IPC分类号： H01L21/265 , H01L21/02 , H01L21/316 , H01L21/768 , H01L23/522 , H01L27/00 , H01L27/10 , H01L27/11 , H01L21/205 , H01L21/285
CPC分类号： H01L28/20 , H01L21/76889 , H01L27/1112
摘要： A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.
摘要翻译：提供一种用于形成半导体集成电路的多晶硅电阻性负载元件的方法和根据该集成电路形成的集成电路。具有第一类型的导电性的轻掺杂的第一导电层。在集成电路上形成第一氧化物层，其中第一开口穿过其暴露第一导电层的一部分。使用第一氧化物层作为掩模，然后用第二导电类型的掺杂剂注入第一导电层的暴露部分，以形成暴露部分和被掩模覆盖的部分之间的结。然后在第一开口中的第一氧化物层的一部分上形成第二氧化物区域，并且在接合处以及暴露的第一导电层的与接合部相邻的部分上形成第二氧化物区域。在第一导电层的暴露部分上形成硅化物。

6. 发明授权

US5244827A Method for planarized isolation for CMOS devices 失效
标题翻译： CMOS器件平面隔离方法
公开(公告)号：US5244827A
公开(公告)日：1993-09-14
申请号：US785774
申请日：1991-10-31
申请人： Girish A. Dixit , Fusen E. Chen , Robert O. Miller
发明人： Girish A. Dixit , Fusen E. Chen , Robert O. Miller
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763 , H01L27/08
CPC分类号： H01L21/763 , H01L21/76224 , Y10S148/05
摘要： A method for forming field oxide regions includes the formation of cavities in a semiconductor substrate. A layer of thermal oxide is then grown on the substrate. A layer of planarizing material is deposited over the device, filling the cavities. The planarizing layer is etched back to expose a portion of the cavities. A conformal layer of undoped oxide or a layer of polycrystalline silicon that is converted to oxide is deposited over the device, followed by a second layer of planarizing material, The planarizing material and conformal layer are then etched back to expose the active areas in the substrate.

7. 发明授权

US5571752A Method of forming a planar contact with a void 失效
标题翻译：与空隙形成平面接触的方法
公开(公告)号：US5571752A
公开(公告)日：1996-11-05
申请号：US370456
申请日：1995-01-09
申请人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
发明人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L21/283
CPC分类号： H01L21/76843 , H01L21/76877 , Y10S257/915
摘要： A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.
摘要翻译：提供了用于图案化集成电路的亚微米半导体层的方法，以及根据该集成电路形成的集成电路。在集成电路上形成第一导电结构。在第一导电结构上形成电介质，其具有暴露下面的第一导电层的一部分的接触开口。阻挡层形成在接触开口的底部。通过化学气相沉积在介电层上形成第二基本上保形的导电层; 沿着接触开口的侧壁和底部。然后在第二导电层上形成第三导电层，其中第三导电层不填充接触开口。第二和第三导电层被蚀刻以形成基本上在接触开口上的互连。

8. 发明授权

US5440166A Planarized isolation structure for CMOS devices 失效
标题翻译： CMOS器件的平面隔离结构
公开(公告)号：US5440166A
公开(公告)日：1995-08-08
申请号：US276039
申请日：1994-07-15
申请人： Girish A. Dixit , Fusen E. Chen , Robert O. Miller
发明人： Girish A. Dixit , Fusen E. Chen , Robert O. Miller
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763 , H01L27/08 , H01L21/473
CPC分类号： H01L21/763 , H01L21/76224 , Y10S148/05
摘要： A field oxide structure is formed within a cavity formed in a semiconductor substrate. The cavity has a U-shaped cross section. A layer of thermal oxide covers the walls and bottom of the cavity, and a region of reflowable glass or spin on glass fills the cavity. A layer of undoped oxide, having an upper surface coplanar with the substrate upper surface is formed over the cavity, so that the spin on or reflowable glass is completely surrounded by either thermal oxide or an undoped oxide layer.
摘要翻译：在形成在半导体衬底中的空腔内形成场氧化物结构。空腔具有U形横截面。一层热氧化物覆盖空腔的壁和底部，玻璃上可旋转的区域或玻璃上的旋转填充空腔。在空腔之上形成具有与基板上表面共面的上表面的未掺杂氧化物层，使得旋转或可回流玻璃被热氧化物或未掺杂的氧化物层完全包围。

9. 发明授权

US5582971A Method of forming submicron contacts 失效
标题翻译：形成亚微米接触的方法
公开(公告)号：US5582971A
公开(公告)日：1996-12-10
申请号：US434371
申请日：1995-05-03
申请人： Fusen E. Chen , Robert O. Miller , Girish A. Dixit
发明人： Fusen E. Chen , Robert O. Miller , Girish A. Dixit
IPC分类号： H01L21/28 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/768
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/76843 , H01L21/76844 , H01L21/76877 , Y10S257/915
摘要： A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.
摘要翻译：提供了用于图案化集成电路的亚微米半导体层的方法，以及根据该集成电路形成的集成电路。在集成电路上形成导体结构。在集成电路上形成介电层。在电介质层中形成接触开口，暴露下面的第一导电结构的一部分。在电介质层和接触开口中形成阻挡层。在阻挡层和接触开口中形成基本上共形的层。共形层被部分蚀刻掉，其中保形层仅保留在接触开口的底部。在阻挡层和剩余的保形层上形成第二导电层。

10. 发明授权

US5182627A Interconnect and resistor for integrated circuits 失效
标题翻译：集成电路的互连和电阻
公开(公告)号：US5182627A
公开(公告)日：1993-01-26
申请号：US769171
申请日：1991-09-30
申请人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
发明人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
IPC分类号： H01L21/265 , H01L21/02 , H01L21/316 , H01L21/768 , H01L23/522 , H01L27/00 , H01L27/10 , H01L27/11
CPC分类号： H01L28/20 , H01L21/76889 , H01L27/1112
摘要： A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.

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