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1. 发明授权

US6130156A Variable doping of metal plugs for enhanced reliability 有权
标题翻译：金属插头的可变掺杂可提高可靠性
公开(公告)号：US6130156A
公开(公告)日：2000-10-10
申请号：US281538
申请日：1999-03-30
申请人： Robert H. Havemann , Girish A. Dixit , Stephen W. Russell
发明人： Robert H. Havemann , Girish A. Dixit , Stephen W. Russell
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/441
CPC分类号： H01L21/76843 , H01L21/76873 , H01L21/76876 , H01L21/76877 , H01L21/76886 , H01L2221/1089 , H01L23/53219 , H01L23/53233 , H01L2924/0002
摘要： A method of fabricating an interconnect wherein there is initially provided a first layer of electrically conductive interconnect (3). A via (7) is formed which is defined by walls extending to the first layer of interconnect. A layer of titanium (9) is formed between the electrically conductive interconnect and the first layer of electrically conductive metal (11). A first layer of electrically conductive metal is formed on the walls of the via having a predetermined etch rate relative to a specific etch species and a second layer of electrically conductive metal (13) is formed on the first layer of electrically conductive metal having an etch rate relative to the specific etch species greater than the first layer and which preferably extends into the via. The first layer of electrically conductive interconnect is preferably aluminum, the first layer of electrically conductive metal is preferably a metal containing from about one percent by weight to about one hundred percent copper and the rest essentially aluminum and the second layer of electrically conductive metal is preferably copper doped aluminum having a lower copper content than the first electrically conductive layer.
摘要翻译：一种制造互连的方法，其中最初提供第一层导电互连（3）。形成通孔（7），其通过延伸到第一互连层的壁限定。在导电互连和导电金属（11）的第一层之间形成一层钛（9）。第一层导电金属形成在通孔的壁上，具有相对于特定蚀刻物质的预定蚀刻速率，并且第二层导电金属（13）形成在具有蚀刻的第一导电金属层上相对于比第一层大的特定蚀刻物质的速率，并且优选地延伸到通孔中。导电互连的第一层优选为铝，第一层导电金属优选为含有约1％至约100％铜的金属，其余基本上为铝，而第二层导电金属优选为铜掺杂的铝的铜含量低于第一导电层。

2. 发明授权

US06358849B1 Integrated circuit interconnect and method 有权
标题翻译：集成电路互连和方法
公开(公告)号：US06358849B1
公开(公告)日：2002-03-19
申请号：US09467680
申请日：1999-12-21
申请人： Robert H. Havemann , Girish A. Dixit , Manoj Jain , Eden Zielinski , Qi-Zhong Hong , Jeffrey West
发明人： Robert H. Havemann , Girish A. Dixit , Manoj Jain , Eden Zielinski , Qi-Zhong Hong , Jeffrey West
IPC分类号： H01L21302
CPC分类号： H01L21/76808 , H01L21/31053 , H01L21/76224 , H01L21/76849 , H01L21/76856 , H01L21/76867
摘要： A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.
摘要翻译：一种双嵌入互连制造方法，在沟槽蚀刻中沟槽蚀刻和去除填充物之后，在通孔中使用临时填料。这在沟槽蚀刻期间通过底部保护提供。

3. 发明授权

US06333265B1 Low pressure, low temperature, semiconductor gap filling process 失效
标题翻译：低压，低温，半导体缺口填充工艺
公开(公告)号：US06333265B1
公开(公告)日：2001-12-25
申请号：US08766199
申请日：1996-12-12
申请人： Girish A. Dixit , Anthony Konecni , Robert H. Havemann
发明人： Girish A. Dixit , Anthony Konecni , Robert H. Havemann
IPC分类号： H01L2144
CPC分类号： H01L21/76882 , H01L21/76838 , H01L21/76843 , H01L21/76862
摘要： A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;
摘要翻译：提供了用于填充诸如触点和通孔的集成电路腔的结构和工艺。这些结构在不超过约300℃，优选在约20°-275℃之间的较低温度下填充，该温度范围允许使用低介电常数（κ）聚合物（即，〜3.0）。优选地，空腔设置有不含钛的衬垫以促进空腔填充，并且空腔填充有CVD铝，其通过在大气压至约50MPa的压力下的强力填充物引入空腔中，并且优选地在约100°-300℃的温度下不超过约30Mpa。以上述方式填充的空腔表现出比通过常规实践填充的结构小至多30％的电阻水平。

4. 发明授权

US06159847A Multilayer metal structure for improved interconnect reliability 有权
标题翻译：多层金属结构，提高互连可靠性
公开(公告)号：US06159847A
公开(公告)日：2000-12-12
申请号：US191027
申请日：1998-11-12
申请人： Robert H. Havemann , Girish A. Dixit
发明人： Robert H. Havemann , Girish A. Dixit
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L21/7685 , H01L21/76843 , H01L21/76877 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： AlCu alloys with higher Cu content are added in thin layers within a metallization structure. The increased Cu content provided by the thin layer improves interconnect reliability and reduces the effects of electromigration with minimal effect on plasma etch and cleanup processes.
摘要翻译：具有较高Cu含量的AlCu合金以金属化结构内的薄层加入。由薄层提供的增加的Cu含量提高了互连可靠性，并且减少电迁移的影响，对等离子体蚀刻和清除过程的影响最小。

5. 发明授权

US06589865B2 Low pressure, low temperature, semiconductor gap filling process 有权
标题翻译：低压，低温，半导体缺口填充工艺
公开(公告)号：US06589865B2
公开(公告)日：2003-07-08
申请号：US09899194
申请日：2001-07-06
申请人： Girish A. Dixit , Anthony Konecni , Robert H. Havemann
发明人： Girish A. Dixit , Anthony Konecni , Robert H. Havemann
IPC分类号： H01L214763
CPC分类号： H01L21/76882 , H01L21/76838 , H01L21/76843 , H01L21/76862
摘要： A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;
摘要翻译：提供了用于填充诸如触点和通孔的集成电路腔的结构和工艺。这些结构在不超过约300℃，优选在约20°-275℃之间的较低温度下填充，该温度范围允许使用低介电常数（κ）聚合物（即，〜3.0）。优选地，空腔设置有元素的无钛衬里以便于空腔填充，并且空腔填充有CVD铝，其通过在大气压至约50MPa的压力下的强力填充物引入空腔中，并且优选地不大约30MPa，在约100°-300℃的温度范围内。以上述方式填充的凹坑表现出比通过常规实践填充的结构低30％的电阻水平。

6. 发明授权

US07425716B2 Method and apparatus for reducing charge density on a dielectric coated substrate after exposure to a large area electron beam 失效
标题翻译：用于在暴露于大面积电子束之后降低电介质涂覆的基底上的电荷密度的方法和装置
公开(公告)号：US07425716B2
公开(公告)日：2008-09-16
申请号：US11414649
申请日：2006-04-27
申请人： Alexandros T. Demos , Khaled A. Elsheref , Yuri Trachuk , Tom K. Cho , Girish A. Dixit , Hichem M'Saad , Derek Witty
发明人： Alexandros T. Demos , Khaled A. Elsheref , Yuri Trachuk , Tom K. Cho , Girish A. Dixit , Hichem M'Saad , Derek Witty
IPC分类号： H02H23/00
CPC分类号： H01J37/317 , H01J2237/0041
摘要： Embodiments in accordance with the present invention relate to a number of techniques, which may be applied alone or in combination, to reduce charge damage of substrates exposed to electron beam radiation. In one embodiment, charge damage is reduced by establishing a robust electrical connection between the exposed substrate and ground. In another embodiment, charge damage is reduced by modifying the sequence of steps for activating and deactivating the electron beam source to reduce the accumulation of charge on the substrate. In still another embodiment, a plasma is struck in the chamber containing the e-beam treated substrate, thereby removing accumulated charge from the substrate. In a further embodiment of the present invention, the voltage of the anode of the e-beam source is reduced in magnitude to account for differences in electron conversion efficiency exhibited by different cathode materials.
摘要翻译：根据本发明的实施例涉及可以单独或组合应用的多种技术，以减少暴露于电子束辐射的衬底的电荷损伤。在一个实施例中，通过在暴露的基板和地之间建立牢固的电连接来减小电荷损伤。在另一个实施例中，通过修改用于激活和去激活电子束源的步骤顺序来减少电荷损伤，以减少电荷在衬底上的累积。在另一个实施例中，在包含电子束处理的衬底的室中撞击等离子体，从而从衬底去除积聚的电荷。在本发明的另一个实施例中，电子束源的阳极的电压的大小被减小以考虑到由不同的阴极材料表现的电子转换效率的差异。

7. 发明授权

US07205228B2 Selective metal encapsulation schemes 失效
标题翻译：选择性金属封装方案
公开(公告)号：US07205228B2
公开(公告)日：2007-04-17
申请号：US10812480
申请日：2004-03-30
申请人： Deenesh Padhi , Srinivas Gandikota , Mehul Naik , Suketu A. Parikh , Girish A. Dixit
发明人： Deenesh Padhi , Srinivas Gandikota , Mehul Naik , Suketu A. Parikh , Girish A. Dixit
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/288 , H01L21/76829 , H01L21/7685 , H01L21/76885
摘要： A method and system of processing a semiconductor substrate includes, in one or more embodiments, depositing a protective layer on the substrate surface comprising a conductive element disposed in a dielectric material; processing the protective layer to expose the conductive element; electrolessly depositing a metallic passivating layer onto the conductive element; and removing at least a portion of the protective layer from the substrate after electroless deposition. In another aspect, a method and system of processing a semiconductor includes depositing a metallic passivating layer onto a substrate surface comprising a conductive element, masking the passivating layer to protect the underlying conductive element of the substrate surface, removing the unmasked passivating layer, and removing the mask from the passivating layer.
摘要翻译：在一个或多个实施例中，处理半导体衬底的方法和系统包括在衬底表面上沉积保护层，所述保护层包括布置在电介质材料中的导电元件; 处理所述保护层以暴露所述导电元件; 将金属钝化层无电沉积到导电元件上; 以及在无电沉积之后从衬底去除保护层的至少一部分。在另一方面，一种处理半导体的方法和系统包括在包括导电元件的衬底表面上沉积金属钝化层，掩蔽钝化层以保护衬底表面的下面的导电元件，去除未屏蔽的钝化层，以及去除掩模从钝化层。

8. 发明授权

US07018941B2 Post treatment of low k dielectric films 有权
标题翻译：后处理低k电介质膜
公开(公告)号：US07018941B2
公开(公告)日：2006-03-28
申请号：US10830203
申请日：2004-04-21
申请人： Zhenjiang Cui , Josephine J. Chang , Alexandros T. Demos , Reza Arghavani , Derek R. Witty , Helen R. Armer , Girish A. Dixit , Hichem M'Saad
发明人： Zhenjiang Cui , Josephine J. Chang , Alexandros T. Demos , Reza Arghavani , Derek R. Witty , Helen R. Armer , Girish A. Dixit , Hichem M'Saad
IPC分类号： H01L21/31 , H01L21/461
CPC分类号： H01L21/31633 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/02351
摘要： A method of depositing a low dielectric constant film on a substrate and post-treating the low dielectric constant film is provided. The post-treatment includes rapidly heating the low dielectric constant film to a desired high temperature and then rapidly cooling the low dielectric constant film such that the low dielectric constant film is exposed to the desired high temperature for about five seconds or less. In one aspect, the post-treatment also includes exposing the low dielectric constant film to an electron beam treatment and/or UV radiation.
摘要翻译：提供了一种在衬底上沉积低介电常数膜并对低介电常数膜进行后处理的方法。后处理包括将低介电常数膜快速加热到期望的高温，然后快速冷却低介电常数膜，使得低介电常数膜暴露于所需的高温约5秒或更短。一方面，后处理还包括将低介电常数膜暴露于电子束处理和/或UV辐射。

9. 发明授权

US06962883B2 Integrated circuit insulator and method 失效
标题翻译：集成电路绝缘子及方法
公开(公告)号：US06962883B2
公开(公告)日：2005-11-08
申请号：US10634413
申请日：2003-08-05
申请人： Somnath S. Nag , Girish A. Dixit , Srikanth Krishnan
发明人： Somnath S. Nag , Girish A. Dixit , Srikanth Krishnan
IPC分类号： H01L21/316 , H01L21/768 , H01L21/31
CPC分类号： H01L21/02164 , H01L21/02131 , H01L21/022 , H01L21/02274 , H01L21/31612 , H01L21/31629 , H01L21/76801
摘要： A two-stage plasma enhance dielectric deposition with a first stage of low capacitively-coupled RF bias with conformal deposition (202) followed by high capacitively-coupled RF bias for planarizing deposition (204) limits the charge build up on the underlying structure (104, 106, 108).
摘要翻译：两阶段等离子体增强具有第一级低电容耦合RF偏压的电介质沉积，其具有适形沉积（202），随后是用于平坦化沉积的高电容耦合RF偏压（204），限制了在下面的结构上的电荷（104），106,108）。

10. 发明授权

US06951599B2 Electropolishing of metallic interconnects 失效
标题翻译：电抛光金属互连
公开(公告)号：US06951599B2
公开(公告)日：2005-10-04
申请号：US10188163
申请日：2002-07-01
申请人： Joseph Yahalom , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
发明人： Joseph Yahalom , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
IPC分类号： C25F3/16 , C25F3/22 , C25F7/00
CPC分类号： C25F3/16 , C25F3/22
摘要： Embodiments of the present invention generally relate to a method and apparatus for planarizing a substrate by electropolishing techniques. Certain embodiments of an electropolishing apparatus include a contact ring adapted to support a substrate, a cell body adapted to hold an electropolishing solution, a fluid supply system adapted to provide the electropolishing solution to the cell body, a cathode disposed within the cell body, a power supply system in electrical communication with the contact ring and the cathode, and a controller coupled to at least the fluid supply system and the power supply system. The controller may be adapted to provide a first set of electropolishing conditions to form a boundary layer between the substrate and the electropolishing solution to an initial thickness and may be adapted to provide a second set of electropolishing conditions to control the boundary layer to a subsequent thickness less than or equal to the initial thickness.
摘要翻译：本发明的实施例一般涉及通过电抛光技术来平坦化衬底的方法和装置。电抛光装置的某些实施例包括适于支撑基底的接触环，适于保持电解抛光溶液的电池体，适于将电解抛光溶液提供给电池体的流体供应系统，设置在电池体内的阴极，电源系统与接触环和阴极电连通，以及控制器，耦合到至少流体供应系统和电源系统。控制器可以适于提供第一组电抛光条件，以在衬底和电解抛光溶液之间形成初始厚度的边界层，并且可适于提供第二组电抛光条件以将边界层控制到随后的厚度小于或等于初始厚度。

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