专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06406945B1 Method for forming a transistor gate dielectric with high-K and low-K regions 有权
标题翻译：用于形成具有高K和低K区的晶体管栅极电介质的方法
公开(公告)号：US06406945B1
公开(公告)日：2002-06-18
申请号：US09769810
申请日：2001-01-26
申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L21335
CPC分类号： H01L29/517 , H01L21/28167 , H01L21/28194 , H01L29/42376 , H01L29/512 , H01L29/518 , H01L29/66583 , Y10S257/90
摘要： A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.
摘要翻译：一种形成具有不同介电常数区域的栅极电介质的方法。在半导体结构上形成虚拟电介质层。图案化虚拟介质层以形成栅极开口。在虚拟电介质上和栅极开口中形成高K电介质层。在高K电介质层上形成低K电介质层。在栅极开口边缘的低K电介质层上形成间隔物。低K电介质层从间隔物之间的栅极开口的底部去除。移除间隔件以形成阶梯式门开口。阶梯式门开口在侧壁和栅极开口底部的边缘处具有高K电介质层和低K电介质层，并且仅在台阶底部中心的高k电介质层开门在阶梯式门开口形成栅电极。

22. 发明授权

US06461900B1 Method to form a self-aligned CMOS inverter using vertical device integration 失效
标题翻译：使用垂直器件集成形成自对准CMOS反相器的方法
公开(公告)号：US06461900B1
公开(公告)日：2002-10-08
申请号：US09981438
申请日：2001-10-18
申请人： Ravi Sundaresan , Yang Pan , James Lee Young Meng , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek
发明人： Ravi Sundaresan , Yang Pan , James Lee Young Meng , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek
IPC分类号： H01L2100
CPC分类号： H01L21/84 , H01L21/823885 , H01L27/1203
摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprises silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.
摘要翻译：实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。

23. 发明授权

US06461887B1 Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth 有权
标题翻译：通过蚀刻沉积蚀刻和选择性外延生长形成倒置阶梯STI结构的方法
公开(公告)号：US06461887B1
公开(公告)日：2002-10-08
申请号：US10038391
申请日：2002-01-03
申请人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
发明人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
IPC分类号： H01L2100
CPC分类号： H01L21/76232
摘要： A method of forming an inverted staircase shaped STI structure comprising the following steps. A semiconductor substrate having an overlying oxide layer is provided. The substrate having at least a pair of active areas defining an STI region therebetween. The oxide layer is etched a first time within the active areas to form first step trenches. The first step trenches having exposed sidewalls. Continuous side wall spacers are formed on said exposed first step trench sidewalls. The oxide layer is etched X+1 more successive times using the previously formed step side wall spacers as masks to form successive step trenches within the active areas. Each of the successive step trenches having exposed sidewalls and have side wall spacers successively formed on the successive step trench exposed sidewalls. The oxide layer is etched a final time using the previously formed step side wall spacers as masks to form final step trenches exposing the substrate within the active areas. The STI region comprising an inverted staircase shaped STI structure. The step side wall spacers are removed from the X+2 step trenches. A planarized active area silicon structure is formed within the X+2 and final step trenches.
摘要翻译：一种形成倒置阶梯状STI结构的方法，包括以下步骤。提供具有上覆氧化物层的半导体衬底。衬底具有至少一对在其间限定STI区的有源区。首先在有源区内蚀刻氧化物层以形成第一级沟槽。第一级沟槽具有暴露的侧壁。连续的侧壁间隔件形成在所述暴露的第一阶梯沟槽侧壁上。使用先前形成的步骤侧壁间隔物作为掩模，将氧化物层连续蚀刻X + 1次，以在有效区域内形成连续的台阶沟槽。每个连续的台阶沟槽具有暴露的侧壁并且具有连续形成在连续的阶梯槽暴露侧壁上的侧壁间隔物。使用先前形成的步骤侧壁间隔物作为掩模来最后蚀刻氧化物层，以形成在活性区域内暴露衬底的最终步骤沟槽。 STI区域包括倒置的阶梯状STI结构。从X + 2台阶沟槽中移除台阶侧壁间隔物。平面化的有源区硅结构形成在X + 2和最后阶梯沟内。

24. 发明授权

US06436774B1 Method for forming variable-K gate dielectric 失效
公开(公告)号：US06436774B1
公开(公告)日：2002-08-20
申请号：US09769811
申请日：2001-01-26
申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L29/42376 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

25. 发明授权

US06403485B1 Method to form a low parasitic capacitance pseudo-SOI CMOS device 有权
标题翻译：形成低寄生电容伪SOI CMOS器件的方法
公开(公告)号：US06403485B1
公开(公告)日：2002-06-11
申请号：US09846177
申请日：2001-05-02
申请人： Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
发明人： Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21302
CPC分类号： H01L21/76895
摘要： A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas. The hard mask layer is removed. Ions are implanted and driven in to form elevated S/D regions within the polysilicon layer adjacent to the gate electrodes to complete formation of transistors having elevated S/D regions.
摘要翻译：描述了一种形成具有可扩展的用于局部互连的源/漏（S / D）区域较高的伪SOI器件的方法。分离相邻有源区的浅沟槽隔离（STI）区域设置在半导体衬底内。多晶硅栅极电极和相关的SID延伸部分在其中硬掩模层覆盖每个栅极电极的有源区域内和衬底上制造。在每个栅电极的侧壁上形成电介质间隔物。沉积覆盖栅电极和衬底的多晶硅层。在硬掩模层上用抛光光阑抛光多晶硅层。多晶硅层被回蚀，由此多晶硅层相对于栅电极凹陷。此后，将多晶硅层蚀刻掉，覆盖STI区域，其中期望相邻的有源区域之间的间隔。如果在相邻的有源区域之间需要局部互连，则多晶硅层不会被覆盖在分离这些有源区域的STI区域之上。去除硬掩模层。离子被植入和驱动以在与栅电极相邻的多晶硅层内形成升高的S / D区，以完成具有升高的S / D区的晶体管的形成。

26. 发明授权

US06303449B1 Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP 失效
标题翻译：通过选择性去除源极/漏极区域中的栅极电介质，然后进行多晶沉积和CMP，形成自对准升高的源极/漏极的方法
公开(公告)号：US06303449B1
公开(公告)日：2001-10-16
申请号：US09713835
申请日：2000-11-16
申请人： Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Kiok Boone Quek , Ravi Sundaresan
发明人： Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Kiok Boone Quek , Ravi Sundaresan
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/2257 , H01L29/66492
摘要： A method of manufacturing a self aligned elevated source/drain (S/D). A first insulating layer is formed over a substrate. The first insulating layer having at least a gate opening and source/drain (S/D) openings adjacent to the gate opening. Spacer portions of the first insulating layer define the gate opening. A gate dielectric layer is formed over the substrate in the gate opening. A conductive layer is formed over the substrate. The conductive layer fills the gate opening and the source/drain (S/D) openings. The conductive layer is doped with dopants. The conductive layer is planarized to form a gate over the gate dielectric layer and filling the gate opening and filling the source/drain (S/D) opening to form elevated source/drain (S/D) regions. The conductive layer is preferably planarized so that the top surface of the conductive layer is level with the top surface of the first insulating layer. The spacer portions are removed to form spacer openings. LDD regions are formed in the substrate in the spacer opening. A dielectric layer is formed over the substrate filling the spacer openings. Source/drain (S/D) regions are formed in the substrate under the elevated source/drain (S/D) regions.
摘要翻译：制造自对准提升源/漏（S / D）的方法。第一绝缘层形成在衬底上。第一绝缘层至少具有与开口相邻的栅极开口和源极/漏极（S / D）开口。第一绝缘层的间隔部分限定了开口。在栅极开口中的衬底上方形成栅极电介质层。导电层形成在衬底上。导电层填充栅极开口和源极/漏极（S / D）开口。导电层掺杂有掺杂剂。导电层被平坦化以在栅极介电层上形成栅极，并填充栅极开口并填充源极/漏极（S / D）开口以形成升高的源极/漏极（S / D）区域。导电层优选被平坦化，使得导电层的顶表面与第一绝缘层的顶表面平齐。间隔部分被去除以形成间隔开口。 LDD区域形成在衬垫开口中的衬底中。介质层形成在填充间隔开口的衬底上。在升高的源极/漏极（S / D）区域的衬底中形成源/漏（S / D）区。

27. 发明申请

US20050009357A1 Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
标题翻译：通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程
公开(公告)号：US20050009357A1
公开(公告)日：2005-01-13
申请号：US10909523
申请日：2004-08-02
申请人： Lap Chan , Sanford Chu , Chit Ng , Purakh Verma , Jia Zheng , Johnny Chew , Choon Sia
发明人： Lap Chan , Sanford Chu , Chit Ng , Purakh Verma , Jia Zheng , Johnny Chew , Choon Sia
IPC分类号： H01L21/20 , H01L21/265 , H01L21/302 , H01L21/461 , H01L21/764
CPC分类号： H01L21/764 , H01L21/26506
摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.
摘要翻译：降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。在所述至少一个上介电层上形成钝化层。图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

28. 发明授权

US07382027B2 MOSFET device with low gate contact resistance 有权
标题翻译：具有低栅极接触电阻的MOSFET器件
公开(公告)号：US07382027B2
公开(公告)日：2008-06-03
申请号：US11045958
申请日：2005-01-28
申请人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
发明人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

29. 发明授权

US06861317B1 Method of making direct contact on gate by using dielectric stop layer 失效
标题翻译：通过使用介电阻挡层在栅极上直接接触的方法
公开(公告)号：US06861317B1
公开(公告)日：2005-03-01
申请号：US10664211
申请日：2003-09-17
申请人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
发明人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作时的噪声性能，增加的单位功率增益频率（fmax）和减小的栅极延迟。

30. 发明授权

US07022578B2 Heterojunction bipolar transistor using reverse emitter window 有权
标题翻译：使用反向发射极窗口的异质结双极晶体管
公开(公告)号：US07022578B2
公开(公告)日：2006-04-04
申请号：US10683713
申请日：2003-10-09
申请人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jian Xun Li , Zhen Jia Zheng
发明人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jian Xun Li , Zhen Jia Zheng
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/41708 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, an intrinsic base region of a compound semiconductive material over the collector region, an extrinsic base region, an emitter structure, an interlevel dielectric layer over the collector region, extrinsic base region and emitter structure, and connections through the interlevel dielectric layer to the base region, the emitter structure, and the collector region. The emitter structure is formed by forming a reverse emitter window over the intrinsic base region, which subsequently is etched to form an emitter window having a multi-layer reverse insulating spacer therein.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，集电极区域上的化合物半导体材料的本征基极区域，非本征基极区域，发射极结构，层间电介质层集电极区域，非本征基极区域和发射极结构以及通过层间介质层到基极区域，发射极结构和集电极区域的连接。通过在本征基极区域上形成反向发射极窗口形成发射极结构，其随后被蚀刻以形成其中具有多层反向绝缘间隔物的发射极窗口。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式