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US06461900B1 Method to form a self-aligned CMOS inverter using vertical device integration 失效
标题翻译：使用垂直器件集成形成自对准CMOS反相器的方法
公开(公告)号：US06461900B1
公开(公告)日：2002-10-08
申请号：US09981438
申请日：2001-10-18
申请人： Ravi Sundaresan , Yang Pan , James Lee Young Meng , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek
发明人： Ravi Sundaresan , Yang Pan , James Lee Young Meng , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek
IPC分类号： H01L2100
CPC分类号： H01L21/84 , H01L21/823885 , H01L27/1203
摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprises silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.
摘要翻译：实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。

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