专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07573081B2 Method to fabricate horizontal air columns underneath metal inductor 有权
标题翻译：在金属电感器下制造水平空气柱的方法
公开(公告)号：US07573081B2
公开(公告)日：2009-08-11
申请号：US11519103
申请日：2006-09-11
申请人： Lap Chan , Kok Wai Johnny Chew , Cher Liang Cha , Chee Tee Chua
发明人： Lap Chan , Kok Wai Johnny Chew , Cher Liang Cha , Chee Tee Chua
IPC分类号： H01L29/78
CPC分类号： H01L21/76834 , H01F3/14 , H01F17/0006 , H01F27/34 , H01F41/041 , H01F41/045 , H01L21/764 , H01L21/7682 , H01L23/5227 , H01L23/53295 , H01L27/08 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.
摘要翻译：提供了一种在硅衬底的表面上形成电感器的新方法。本发明提供金属电感器下面的氧化物鳍片的覆盖层。氧化物鳍片为上覆的金属电感器提供了稳定的支持，同时也允许水平空气柱同时存在于电感器下面。通过重复施用所使用的掩模，可以在本发明的基础上产生空间上插入在所产生的氧化物翅片的覆盖层之间的空腔的覆盖层。衬底表面上的空穴的存在显着降低了与衬底相关联的电感器的寄生电容和串联电阻。

22. 发明授权

US07105420B1 Method to fabricate horizontal air columns underneath metal inductor 有权
公开(公告)号：US07105420B1
公开(公告)日：2006-09-12
申请号：US09413177
申请日：1999-10-07
申请人： Lap Chan , Kok Wai Johnny Chew , Cher Liang Cha , Chee Tee Chua
发明人： Lap Chan , Kok Wai Johnny Chew , Cher Liang Cha , Chee Tee Chua
IPC分类号： H01L21/76
CPC分类号： H01L21/76834 , H01F3/14 , H01F17/0006 , H01F27/34 , H01F41/041 , H01F41/045 , H01L21/764 , H01L21/7682 , H01L23/5227 , H01L23/53295 , H01L27/08 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

23. 发明授权

US06326272B1 Method for forming self-aligned elevated transistor 失效
标题翻译：用于形成自对准高架晶体管的方法
公开(公告)号：US06326272B1
公开(公告)日：2001-12-04
申请号：US09442496
申请日：1999-11-18
申请人： Lap Chan , Cher Liang Cha
发明人： Lap Chan , Cher Liang Cha
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/28123 , H01L29/0653 , H01L29/665 , H01L29/66553 , H01L29/66651
摘要： A method of forming a self-aligned elevated transistor using selective epitaxial growth is described. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having a lower portion contacting the substrate and an upper portion having a width larger than the width of the lower portion. A silicon layer is grown within the trench using selective epitaxial growth wherein the silicon layer fills the lower portion and partially fills the upper portion. Nitride spacers are formed on the sidewalls of the trench. A polysilicon layer is deposited overlying the oxide layer and within the trench and etched back to form a gate electrode within the trench between the nitride spacers. The nitride spacers are etched away where they are not covered by the gate electrode leaving thin nitride spacers on sidewalls of the gate electrode. Ions are implanted into the silicon layer exposed at the edges of the trench whereby source and drain pockets are formed within the silicon layer wherein the junction depth is determined by the thickness of the silicon layer. A dielectric layer is deposited overlying the oxide layer and the gate electrode and source/drain pockets within the trench to complete formation of the self-aligned elevated transistor in the fabrication of an integrated circuit.
摘要翻译：描述了使用选择性外延生长形成自对准升高的晶体管的方法。设置覆盖在半导体衬底上的氧化物层。氧化层被蚀刻到半导体衬底上以形成具有与衬底接触的下部的沟槽和具有大于下部宽度的宽度的上部的沟槽。使用选择性外延生长在沟槽内生长硅层，其中硅层填充下部并部分填充上部。氮化物间隔物形成在沟槽的侧壁上。沉积覆盖氧化物层并在沟槽内的多晶硅层被回蚀刻以在氮化物间隔物之间的沟槽内形成栅电极。蚀刻氮化物间隔物，在那里它们不被栅极电极覆盖，从而在栅电极的侧壁上留下薄的氮化物间隔物。将离子注入暴露在沟槽边缘处的硅层中，从而在硅层内形成源极和漏极穴，其中结深度由硅层的厚度确定。沉积覆盖在沟槽内的氧化物层和栅电极和源极/漏极腔的电介质层，以在集成电路的制造中完成自对准升高的晶体管的形成。

24. 发明授权

US6051467A Method to fabricate a large planar area ONO interpoly dielectric in flash device 失效
标题翻译：在闪光装置中制造大平面区域ONO内部电介质的方法
公开(公告)号：US6051467A
公开(公告)日：2000-04-18
申请号：US53855
申请日：1998-04-02
申请人： Lap Chan , Cher Liang Cha
发明人： Lap Chan , Cher Liang Cha
IPC分类号： H01L21/28 , H01L29/423 , H01L21/8247
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A new method of fabricating a stacked gate Flash EEPROM device having an improved interpoly oxide layer is described. A gate oxide layer is provided on the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate oxide layer. The first polysilicon layer is etched away where it is not covered by a mask to form a floating gate. Source and drain regions associated with the floating gate are formed within the substrate. An oxide layer is deposited overlying the floating gate and the substrate. The oxide layer is polished away until the top of the oxide layer is even with the top of the floating gate. A second polysilicon layer is deposited overlying the oxide layer and the first polysilicon layer of the floating gate wherein the second polysilicon layer has a smooth surface. An interpoly dielectric layer is deposited overlying the second polysilicon layer. A third polysilicon layer is deposited overlying the interpoly dielectric layer. The third polysilicon layer and the interpoly dielectric layer are etched away where they are not covered by a mask to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.
摘要翻译：描述了一种制造具有改进的叠层氧化物层的堆叠栅极快闪EEPROM器件的新方法。在半导体衬底的表面上设置栅氧化层。沉积在栅极氧化物层上的第一多晶硅层。第一多晶硅层被蚀刻掉，其未被掩模覆盖以形成浮动栅极。与浮栅相关联的源区和漏区形成在衬底内。沉积在浮动栅极和衬底上的氧化物层。将氧化物层抛光直到氧化物层的顶部与浮动栅极的顶部均匀。第二多晶硅层沉积在覆盖氧化物层和浮置栅极的第一多晶硅层上，其中第二多晶硅层具有光滑表面。沉积在第二多晶硅层上的多层介电层。第三多晶硅层沉积在层间介电层上。第三多晶硅层和多晶硅间介电层被蚀刻掉，其中它们不被掩模覆盖以形成覆盖浮栅的控制栅极。绝缘层沉积在氧化层和控制栅上。通过绝缘层到底层控制栅极和底层的源极和漏极区域形成接触开口。接触开口填充有导电层以完成闪速EEPROM装置的制造。

25. 发明授权

US06878623B2 Technique to achieve thick silicide film for ultra-shallow junctions 失效
标题翻译：实现超浅结的厚硅化物薄膜技术
公开(公告)号：US06878623B2
公开(公告)日：2005-04-12
申请号：US10457885
申请日：2003-06-09
申请人： Cheng Cheh Tan , Randall Cher Liang Cha , Alex See , Lap Chan
发明人： Cheng Cheh Tan , Randall Cher Liang Cha , Alex See , Lap Chan
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L29/66507 , H01L29/41783 , H01L29/665 , H01L29/6656
摘要： A gate structure having associated (LDD) regions and source and drain is formed as is conventional. A first oxide spacer, for example, is formed along the sidewalls of the gate structure. A layer of metal such as titanium is then deposited over the surface of the gate structure. Second sidewall spacers are formed covering the metal over the first sidewall spacer and covering the metal over isolation regions. A layer of polysilicon is deposited over the surface of the gate structure. A rapid thermal annealing (RTA) is performed causing the metal to react with both the silicon in the junction below the metal and the polysilicon above the metal forming a metal silicide. Metal along the sidewalls between the first and second sidewall spacers and over the isolation regions does not react and is etched away. By providing an additional source of silicon in the polysilicon layer above the metal, a thicker silicide is achieved.
摘要翻译：具有相关联（LDD）区域和源极和漏极的栅极结构如常规形成。例如，沿着栅极结构的侧壁形成第一氧化物间隔物。然后在栅极结构的表面上沉积诸如钛的金属层。形成第二侧壁间隔物，覆盖第一侧壁间隔物上的金属，并将金属覆盖在隔离区上。在栅极结构的表面上沉积多晶硅层。进行快速热退火（RTA），使得金属与金属之下的结中的硅和形成金属硅化物的金属上方的多晶硅反应。沿着第一和第二侧壁间隔物之间的侧壁以及隔离区域上的金属不会反应并被蚀刻掉。通过在金属上方的多晶硅层中提供附加的硅源，可获得更厚的硅化物。

26. 发明授权

US06566209B2 Method to form shallow junction transistors while eliminating shorts due to junction spiking 失效
公开(公告)号：US06566209B2
公开(公告)日：2003-05-20
申请号：US09943307
申请日：2001-08-31
申请人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
发明人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/28044 , H01L29/41775 , H01L29/41783 , H01L29/456 , H01L29/4916 , H01L29/4941 , H01L29/665 , H01L29/66545
摘要： A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions. The second electrode layer is etched through to form separate conductive connections. An intermetal dielectric layer is deposited. The intermetal dielectric layer is etched through to form contact openings. A metal layer is deposited and etched through to form separate metal interconnects. A passivation layer is deposited, and the integrated circuit is completed.

27. 发明授权

US06501122B1 Flash device having a large planar area ono interpoly dielectric 失效
标题翻译：具有大的平面区域的多层电介质的闪光装置
公开(公告)号：US06501122B1
公开(公告)日：2002-12-31
申请号：US09534166
申请日：2000-03-24
申请人： Lap Chan , Cher Liang Cha
发明人： Lap Chan , Cher Liang Cha
IPC分类号： H01L29788
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A new method of fabricating a stacked gate Flash EEPROM device having an improved interpoly oxide layer is described. A gate oxide layer is provided on the surface of a substrate. A first polysilicon layer is deposited overlying the gate oxide layer and patterned to form a floating gate. Source and drain regions associated with the floating gate are formed within the substrate. An oxide layer is deposited overlying the floating gate and the substrate. The oxide layer is polished away until the top of the oxide layer is even with the top of the floating gate. A second polysilicon layer is deposited overlying the oxide layer and the first polysilicon layer of the floating gate wherein the second polysilicon layer has a smooth surface. An interpoly dielectric layer is deposited overlying the second polysilicon layer. A third polysilicon layer is deposited overlying the interpoly dielectric layer. The third polysilicon layer and the interpoly dielectric layer are patterned to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.
摘要翻译：描述了一种制造具有改进的叠层氧化物层的堆叠栅极快闪EEPROM器件的新方法。栅极氧化层设置在衬底的表面上。第一多晶硅层沉积在栅极氧化物层上并被图案化以形成浮栅。与浮栅相关联的源区和漏区形成在衬底内。沉积在浮动栅极和衬底上的氧化物层。将氧化物层抛光直到氧化物层的顶部与浮动栅极的顶部均匀。第二多晶硅层沉积在覆盖氧化物层和浮置栅极的第一多晶硅层上，其中第二多晶硅层具有光滑表面。沉积在第二多晶硅层上的多层介电层。第三多晶硅层沉积在层间介电层上。图案化第三多晶硅层和互聚电介质层以形成覆盖浮置栅极的控制栅极。绝缘层沉积在氧化层和控制栅上。通过绝缘层到底层控制栅极和底层的源极和漏极区域形成接触开口。接触开口填充有导电层以完成闪速EEPROM装置的制造。

28. 发明授权

US06483148B2 Self-aligned elevated transistor 有权
标题翻译：自对准高架晶体管
公开(公告)号：US06483148B2
公开(公告)日：2002-11-19
申请号：US10060818
申请日：2002-02-01
申请人： Lap Chan , Cher Liang Cha
发明人： Lap Chan , Cher Liang Cha
IPC分类号： H01L2701
CPC分类号： H01L29/66583 , H01L21/28123 , H01L29/0653 , H01L29/665 , H01L29/66553 , H01L29/66651
摘要： A method of forming a self-aligned elevated transistor using selective epitaxial growth is described. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having a lower portion contacting the substrate and an upper portion having a width larger than the width of the lower portion. A silicon layer is grown within the trench using selective epitaxial growth wherein the silicon layer fills the lower portion and partially fills the upper portion. Nitride spacers are formed on the sidewalls of the trench. A polysilicon layer is deposited overlying the oxide layer and within the trench and etched back to form a gate electrode within the trench between the nitride spacers. The nitride spacers are etched away where they are not covered by the gate electrode leaving thin nitride spacers on sidewalls of the gate electrode. Ions are implanted into the silicon layer exposed at the edges of the trench whereby source and drain pockets are formed within the silicon layer wherein the junction depth is determined by the thickness of the silicon layer. A dielectric layer is deposited overlying the oxide layer and the gate electrode and source/drain pockets within the trench to complete formation of the self-aligned elevated transistor in the fabrication of an integrated circuit.
摘要翻译：描述了使用选择性外延生长形成自对准升高的晶体管的方法。设置覆盖在半导体衬底上的氧化物层。氧化层被蚀刻到半导体衬底上以形成具有与衬底接触的下部的沟槽和具有大于下部宽度的宽度的上部的沟槽。使用选择性外延生长在沟槽内生长硅层，其中硅层填充下部并部分填充上部。氮化物间隔物形成在沟槽的侧壁上。沉积覆盖氧化物层并在沟槽内的多晶硅层被回蚀刻以在氮化物间隔物之间的沟槽内形成栅电极。蚀刻氮化物间隔物，在那里它们不被栅极电极覆盖，从而在栅电极的侧壁上留下薄的氮化物间隔物。将离子注入暴露在沟槽边缘处的硅层中，从而在硅层内形成源极和漏极穴，其中结深度由硅层的厚度确定。沉积覆盖在沟槽内的氧化物层和栅电极和源极/漏极腔的电介质层，以在集成电路的制造中完成自对准升高的晶体管的形成。

29. 发明授权

US06432797B1 Simplified method to reduce or eliminate STI oxide divots 失效
标题翻译：简化方法来减少或消除STI氧化层
公开(公告)号：US06432797B1
公开(公告)日：2002-08-13
申请号：US09768487
申请日：2001-01-25
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
IPC分类号： H01L2176
CPC分类号： H01L21/76237 , H01L21/31053 , H01L21/31055
摘要： A method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. Nitrogen atoms are implanted into the oxide layer overlying the trench. The substrate is annealed whereby a layer of nitrogen-rich oxide is formed at the surface of the oxide layer overlying the trench. The oxide layer is planarized to the semiconductor substrate wherein the nitrogen-rich oxide layer is planarized more slowly than the oxide layer resulting in a portion of the oxide layer remaining overlying the trench after the oxide layer overlying the semiconductor substrate has been removed wherein the portion of the oxide layer remaining provides a smooth transition between the shallow trench isolation and the active areas completing the formation of shallow trench isolation in the fabrication of an integrated circuit device.
摘要翻译：描述了形成浅沟槽隔离的方法，其中在隔离和有源区的边缘处的氧化物凹陷被减少或消除。将沟槽蚀刻到半导体衬底中。沉积在半导体衬底上并填充沟槽的氧化物层。将氮原子注入到覆盖沟槽的氧化物层中。将衬底退火，由此在覆盖沟槽的氧化物层的表面上形成一层富氮氧化物。氧化物层平坦化到半导体衬底，其中富氧氧化物层平坦化比氧化物层缓慢，导致一部分氧化物层保留在沟槽上方，在氧化物层覆盖半导体衬底之后，其中部分剩余的氧化物层在浅沟槽隔离和有源区域之间提供平滑的过渡，从而在集成电路器件的制造中完成浅沟槽隔离的形成。

30. 发明授权

US06387784B1 Method to reduce polysilicon depletion in MOS transistors 失效
标题翻译：减少MOS晶体管多晶硅耗尽的方法
公开(公告)号：US06387784B1
公开(公告)日：2002-05-14
申请号：US09810121
申请日：2001-03-19
申请人： Yung Fu Chong , Randall Cher Liang Cha , Lap Chan , Kin Leong Pey
发明人： Yung Fu Chong , Randall Cher Liang Cha , Lap Chan , Kin Leong Pey
IPC分类号： H01L214763
CPC分类号： H01L29/6656 , H01L21/76886
摘要： A method is provided to reduce poly depletion in MOS transistors. Conventionally, after a polysilicon electrode has been doped, an anneal step is usually performed to activate the dopants. However, the anneal step may be insufficient to drive the implanted impurities down the entire depth of the polysilicon electrode. Consequently, a portion of the polysilicon gate nearest to the gate oxide will be depleted of dopants. This poly depletion will have a detrimental effect on the control of the threshold voltage, and hence on the performance of the device. It is disclosed in the present invention a method of forming polysilicon gates where dopant depletion at the interface near the gate oxide layer is alleviated substantially by using laser annealing; however, by first pre-amorphizing the polycrystalline silicon prior to ion (implantation to a desired depth such that during laser annealing the dopants will diffuse uniformly to a melt depth. In this manner, poly depletion effect is greatly reduced and hence performance of the device improved. The disclosed method is applicable to both n+ doped polysilicon gates (NMOS) and p+ doped polysilicon gates (PMOS).
摘要翻译：提供了一种减少MOS晶体管多余耗尽的方法。通常，在掺杂多晶硅电极之后，通常进行退火步骤以激活掺杂剂。然而，退火步骤可能不足以在多晶硅电极的整个深度下驱动注入的杂质。因此，最接近栅极氧化物的多晶硅栅极的一部分将耗尽掺杂剂。这种多余耗尽将对阈值电压的控制以及因此对器件的性能具有不利影响。在本发明中公开了一种形成多晶硅栅极的方法，其中在栅极氧化物层附近的界面处的掺杂剂消耗基本上通过使用激光退火得到缓解; 然而，通过在离子之前首先将多晶硅预先失配（植入到期望的深度，使得在激光退火期间，掺杂剂将均匀地扩散到熔体深度），以这种方式，多余的效应被大大降低，因此器件的性能所公开的方法适用于n +掺杂多晶硅栅极（NMOS）和p +掺杂多晶硅栅极（PMOS）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式