专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US6073182A Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic 失效
标题翻译：使用全局挂起脉冲逻辑解决多处理器中竞争请求之间的死锁的方法
公开(公告)号：US6073182A
公开(公告)日：2000-06-06
申请号：US70664
申请日：1998-04-30
申请人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
发明人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
IPC分类号： G06F13/16 , G06F15/16 , G06F15/173
CPC分类号： G06F13/1663
摘要： A method using a global hang pulse logic mechanism detects and resolves deadlocks among requesters to the storage controller of a symmetric multiprocessor system in which multiple central processors and I/O adapters are connected to one or more shared storage controllers. Deadlocks may occur in such a system due to specific sequences of requests, either because high priority requests use priority cycles and lock out low priority requests, or because requests of any priority level make resources needed for the completion of other requests too busy. The mechanism logic monitors the length of time a request has been valid in the storage controller without completing, by checking the request register valid bits, and by utilizing a timed pulse which is a subset of the pulse used to detect hangs within the storage controller. If the valid bit is reset at any time detection logic and an internal hang detect latch is set, Logic which allows requests in progress to complete, and holds new requests in an inactive state is activated when the internal hang latch is set and remains active until the request which detected the internal hang is able to complete, thus resetting the internal hang detect latch.
摘要翻译：使用全局挂起脉冲逻辑机制的方法检测并解决请求者之间的死锁到其中多个中央处理器和I / O适配器连接到一个或多个共享存储控制器的对称多处理器系统的存储控制器。由于高优先级请求使用优先级周期并锁定低优先级请求，或者由于任何优先级的请求使得完成其他请求太繁忙所需的资源，因此在这种系统中可能会由于特定的请求序列而在这样的系统中发生死锁。机制逻辑监视存储控制器中的请求已经有效的时间长度，而不需要通过检查请求寄存器有效位以及利用作为用于检测存储控制器内的挂起的脉冲的子集的定时脉冲来完成。如果有效位在任何时候被复位，则检测逻辑和内部挂起检测锁存器被置位，当内部挂起锁存器被设置并且保持有效时，激活允许正在进行中的请求完成并保持处于非活动状态的新请求的逻辑，直到检测到内部挂起的请求能够完成，从而重置内部挂起检测锁存器。

22. 发明授权

US08560776B2 Method for expediting return of line exclusivity to a given processor in a symmetric multiprocessing data processing system 失效
标题翻译：在对称多处理数据处理系统中加速线路排他性返回到给定处理器的方法
公开(公告)号：US08560776B2
公开(公告)日：2013-10-15
申请号：US12021403
申请日：2008-01-29
申请人： Garrett M. Drapala , Pak-kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Garrett M. Drapala , Pak-kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A method and apparatus for eliminating, in a multi-nodes data handling system, contention for exclusivity of lines in cache memory through improved management of system buses, processor cross-invalidate stacks, and the system operations that can lead to these requested cache operations being rejected.
摘要翻译：一种用于在多节点数据处理系统中消除通过改进的系统总线管理，处理器交叉无效堆栈以及可导致这些所请求的高速缓存操作的系统操作的高速缓冲存储器中线路排他性的争用的方法和装置拒绝。

23. 发明授权

US07634708B2 Relocatable storage protect keys for system main memory 有权
标题翻译：系统主存储器的可重定位存储保护键
公开(公告)号：US07634708B2
公开(公告)日：2009-12-15
申请号：US11532294
申请日：2006-09-15
申请人： Kevin W. Kark , Liyong Wang , Carl B. Ford, III , Pak-kin Mak
发明人： Kevin W. Kark , Liyong Wang , Carl B. Ford, III , Pak-kin Mak
IPC分类号： G06F11/00
CPC分类号： G06F12/1475 , G06F11/08
摘要： Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-detect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.
摘要翻译：存储保护密钥和系统数据共享相同的物理存储。关键区域是通过固件动态重新定位。配置阵列用于将关键区域的绝对地址映射到其物理地址。即使键的物理位置被重新定位到不同的区域，键的绝对地址也可以被固定。三重检测双正确ECC方案用于保护密钥。 ECC方案与存储中的常规数据不同，可用于检测非法访问。额外的固件和硬件也旨在限制客户的应用程序直接访问密钥。在可重新定位关键区域的情况下，固件可以将密钥区域从存储器中的已知故障区域移开，以改善系统RAS。我们还实现了共同目标，即密钥存储设备可以与不使用密钥的其他服务器系统使用相同的存储设备。

24. 发明申请

US20090210629A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SELECTIVELY PURGING CACHE ENTRIES 审中-公开
标题翻译：方法，系统和计算机程序产品，用于选择高速缓存进入
公开(公告)号：US20090210629A1
公开(公告)日：2009-08-20
申请号：US12032058
申请日：2008-02-15
申请人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
发明人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A method, system and computer program product for selectively purging entries in a cache of a computer system. The method includes determining a starting storage address and a length of the storage address range to be purged, determining preset values for a congruence class and a compartment of a cache directory, accessing the cache directory based on the preset value of the congruence class, and selecting an entry in the cache directory based on the preset value of the compartment, determining validity of the entry accessed by examining an ownership tag of the entry, comparing a line address of the entry with the starting storage address and a sum of the starting storage address and the length of the storage address range, and selectively purging the entry based on the comparison result.
摘要翻译：一种用于选择性地清除计算机系统的高速缓存中的条目的方法，系统和计算机程序产品。该方法包括确定要清除的存储地址范围的起始存储地址和长度，确定高速缓存目录的同余类和隔间的预设值，基于同余类的预设值访问高速缓存目录;以及基于所述隔室的所述预设值来选择所述缓存目录中的条目，通过检查所述条目的所有权标签来确定所访问的条目的有效性，将所述条目的行地址与所述起始存储地址进行比较，以及所述起始存储器地址和存储地址范围的长度，并且基于比较结果选择性地清除条目。

25. 发明授权

US07577795B2 Disowning cache entries on aging out of the entry 失效
标题翻译：在条目中老化的缓存条目不起作用
公开(公告)号：US07577795B2
公开(公告)日：2009-08-18
申请号：US11339196
申请日：2006-01-25
申请人： David S. Hutton , Kathryn M. Jackson , Keith N. Langston , Pak-kin Mak , Chung-Lung K. Shum
发明人： David S. Hutton , Kathryn M. Jackson , Keith N. Langston , Pak-kin Mak , Chung-Lung K. Shum
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F12/0811 , G06F12/12
摘要： Portions of data in a processor system are stored in a slower main memory and are transferred to a faster memory comprising a hierarchy of cache structures between one or more processors and the main memory. For a system with shared L2 cache(s) between the processor(s) and the main memory, an individual L1 cache of a processor must first communicate to an associated L2 cache(s), or check with such L2 cache(s), to obtain a copy of a particular line from a given cache location prior to, or upon modification, or appropriation of data at a given cached location. The individual L1 cache further includes provisions for notifying the L2 cache(s) upon determining when the data stored in the particular cache line in the L1 cache has been replaced, and when the particular cache line is disowned by an L1 cache, the L2 cache is updated to change the state of the particular cache line therein from an ownership state of exclusive to a particular identified CPU to an ownership state of exclusive to no CPU, thereby allowing reduction of cross interrogate delays during another processor acquisition of the same cache line.
摘要翻译：处理器系统中的数据部分存储在较慢的主存储器中，并被传送到包括一个或多个处理器与主存储器之间的高速缓存结构层级的更快的存储器。对于在处理器和主存储器之间具有共享L2高速缓存的系统，处理器的单个L1高速缓存必须首先通信到相关联的L2高速缓存，或者与这样的L2高速缓存进行检查，在给定的高速缓存位置之前或之后，在给定的高速缓存位置处获取特定行的副本，或者在修改之后获得数据的占用。单独的L1高速缓存还包括用于在确定何时存储在L1高速缓存中的特定高速缓存行中的数据已经被替换的情况下通知L2高速缓存，并且当特定高速缓存行被L1高速缓存取消时，L2高速缓存被更新为将其中的特定高速缓存行的状态从独占的所有权状态改变为特定的所识别的CPU到不属于CPU的独占的所有权状态，从而允许在对同一高速缓存行的另一个处理器采集期间减少交叉询问延迟。

26. 发明申请

US20080071990A1 Method for Ensuring Fairness Among Requests Within a Multi-Node Computer System 有权
标题翻译：确保多节点计算机系统内的请求之间公平的方法
公开(公告)号：US20080071990A1
公开(公告)日：2008-03-20
申请号：US11532156
申请日：2006-09-15
申请人： Craig R Walters , Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak
发明人： Craig R Walters , Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0815
摘要： A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed successfully. By providing the alternate valid bits the dual set of resource valids for each remote requester is provided for each remote requester, where one set of valids indicates if the resource is valid and actively working on the line, and the other set of valids indicates if the resource was valid but encountered some conflict that requires resolution before the request can complete. Only on successful reload and completion of the remote operation does this alternate address valid bit reset and open the way for any pending interface requests to proceed, so all outstanding requests currently loaded in a local resource within the nest system are able to complete before new interface requests are allowed into the system.
摘要翻译：使用包括常规位集合和备用有效位集合的双重有效位集合的方法，其阻止对给定高速缓存行的新请求进入多节点计算机系统的嵌套系统，直到对给定高速缓存行的所有请求已经完成为止成功了通过提供替代的有效位，为每个远程请求者提供用于每个远程请求者的两组资源代码，其中一组代码指示资源是否有效并且在该行上主动地工作，而另一组代码指示是否资源有效，但在请求完成之前遇到一些需要解决的冲突。只有在成功重新加载和完成远程操作时，这个备用地址有效位复位，并为任何待处理的接口请求继续进行打开方式，因此当前加载到嵌套系统中的本地资源的所有未完成的请求都可以在新界面之前完成请求被允许进入系统。

27. 发明授权

US07085898B2 Coherency management for a “switchless” distributed shared memory computer system 失效
标题翻译： “无切换”分布式共享内存计算机系统的一致性管理
公开(公告)号：US07085898B2
公开(公告)日：2006-08-01
申请号：US10435776
申请日：2003-05-12
申请人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
发明人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
IPC分类号： G06F12/00 , G06F15/167 , H04L12/43
CPC分类号： G06F12/0813 , G06F12/0831
摘要： An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are launched onto the ring topology simultaneously in both directions. As the messages traverse the nodes on the ring, they trigger remote controllers to perform coherent actions such as cache accesses or directory updates. Messages arriving on each node from both directions are combined with each other and with locally generated responses to form cumulative final responses. Additionally, controllers on the requesting node may perform local coherent actions based on the information conveyed by the returning final responses. Overall system coherency is maintained through the use of a dual token based scheme which provide coherency points to permit multiple non-contending requests for the same data unit. The cache coherency methods described herein further ensure the latest copy of data is always accessed or modified even when multiple copies are present throughout the multi-nodal system structure. Traditional cache management states are extended to include Intervention Master and Multiple Copy status which minimize overall bus utilization. A novel ring protocol is contemplated which efficiently packages coherency information into bus operational responses that also allow simultaneous data transfers in the direction of minimal latency.
摘要翻译：公开了一种用于管理具有多个节点的对称多处理环境中的存储一致性的装置和方法，每个节点包含多个处理器，I / O适配器，主存储器和包括具有顶级缓存的集成开关的系统控制器。节点通过双同心环拓扑互连。任何给定节点上的本地控制器代表该节点上的所述处理器和I / O适配器启动总线操作。 Snoop请求在两个方向同时发送到环形拓扑上。当消息遍历环上的节点时，它们触发远程控制器执行诸如缓存访问或目录更新之类的一致操作。从两个方向到达每个节点的消息彼此组合并且具有本地生成的响应以形成累积的最终响应。此外，请求节点上的控制器可以基于返回的最终响应传达的信息来执行本地一致的动作。通过使用基于双令牌的方案来维护总体系统一致性，其提供相干点以允许对相同数据单元的多个非竞争请求。本文所述的高速缓存一致性方法进一步确保即使在整个多节点系统结构中存在多个副本，始终访问或修改数据的最新副本。传统的缓存管理状态被扩展到包括干预主机和复制状态，从而最大限度地减少总线总线利用率。考虑了一种新颖的环路协议，其有效地将一致性信息包装到总线操作响应中，其也允许以最小延迟的方向同时进行数据传输。

28. 发明授权

US06079013A Multiprocessor serialization with early release of processors 失效
标题翻译：多处理器串行化与早期版本的处理器
公开(公告)号：US06079013A
公开(公告)日：2000-06-20
申请号：US70429
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F9/52 , G06F9/318 , G06F12/06
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3017
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

29. 发明授权

US08131945B2 Disowning cache entries on aging out of the entry 有权
标题翻译：在条目中老化的缓存条目不起作用
公开(公告)号：US08131945B2
公开(公告)日：2012-03-06
申请号：US12435468
申请日：2009-05-05
申请人： David S. Hutton , Kathryn M. Jackson , Keith N. Langston , Pak-kin Mak , Chung-Lung K. Shum
发明人： David S. Hutton , Kathryn M. Jackson , Keith N. Langston , Pak-kin Mak , Chung-Lung K. Shum
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F12/0811 , G06F12/12
摘要： Caching where portions of data are stored in slower main memory and are transferred to faster memory between one or more processors and the main memory. The cache is such that an individual cache system must communicate to other associated cache systems, or check with such cache systems, to determine if they contain a copy of a given cached location prior to or upon modification or appropriation of data at a given cached location. The cache further includes provisions for determining when the data stored in a particular memory location may be replaced.
摘要翻译：缓存数据的一部分存储在较慢的主存储器中，并被传送到一个或多个处理器与主存储器之间的更快的存储器。高速缓存使得单个高速缓存系统必须与其他相关联的高速缓存系统通信，或者与这种高速缓存系统进行检查，以确定它们是否在给定的高速缓存位置修改或占用数据之前或之后包含给定缓存位置的副本。高速缓存还包括用于确定何时可以替换存储在特定存储器位置中的数据的规定。

30. 发明申请

US20110320862A1 Edram Macro Disablement in Cache Memory 失效
标题翻译：缓存中的Edram宏禁用
公开(公告)号：US20110320862A1
公开(公告)日：2011-12-29
申请号：US12822367
申请日：2010-06-24
申请人： Michael Blake , Timothy C. Bronson , Hieu T. Huynh , Pak-kin Mak
发明人： Michael Blake , Timothy C. Bronson , Hieu T. Huynh , Pak-kin Mak
IPC分类号： G06F11/27 , G06F11/20 , G06F11/00
CPC分类号： G11C29/08 , G06F11/1666 , G06F11/20 , G11C11/401 , G11C29/883 , G11C2029/0401
摘要： Embedded dynamic random access memory (EDRAM) macro disablement in a cache memory includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows, iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro, determining if an error occurred during the testing, and disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining.
摘要翻译：高速缓冲存储器中的嵌入式动态随机存取存储器（EDRAM）宏禁用包括隔离高速缓存存储体的EDRAM宏，高速缓存存储体被划分成多个EDRAM宏的至少三行，所述EDRAM宏与一个至少三行，迭代地测试EDRAM宏的每一行，测试包括尝试在EDRAM宏的每一行进行至少一次写操作，确定在测试期间是否发生错误，以及禁止整行的写操作的基于确定的EDRAM宏相关联的EDRAM宏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式