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11. 发明授权

US06613652B2 Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance 失效
公开(公告)号：US06613652B2
公开(公告)日：2003-09-02
申请号：US09805707
申请日：2001-03-14
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L2130
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76289 , H01L21/764 , H01L27/12
摘要： A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.

12. 发明授权

US06468880B1 Method for fabricating complementary silicon on insulator devices using wafer bonding 失效
标题翻译：使用晶片接合制造绝缘体上互补硅的方法
公开(公告)号：US06468880B1
公开(公告)日：2002-10-22
申请号：US09805954
申请日：2001-03-15
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L2130
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , Y10S438/977
摘要： A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e.g., STI) that fill first trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions. Next, the stop layer is removed. Lastly, devices are formed in and on the active regions.
摘要翻译：一种使用晶片接合形成绝缘体上硅（SOI）器件的方法。提供第一基板，其在第一侧上具有绝缘层。提供了第二衬底，其具有填充第二衬底中的第一沟槽的第一隔离区域（例如STI）。接下来，通过将绝缘层粘合到第一隔离区域和第二基板上，将第一和第二基板结合在一起。然后，在第二基板的第二侧上形成止挡层。图案化第二基板的阻挡层和第二侧，以在第二基板中形成第二沟槽。第二沟槽具有由隔离区域至少部分地限定的侧壁，并且第二沟槽露出第二绝缘层。第二沟槽限定第一隔离区域（STI）上的第一有源区，并在绝缘层上限定第二有源区。接下来，第二沟槽用绝缘体材料填充到第二隔离区域。接下来，停止层被去除。最后，在活动区域中形成器件。

13. 发明授权

US06432797B1 Simplified method to reduce or eliminate STI oxide divots 失效
标题翻译：简化方法来减少或消除STI氧化层
公开(公告)号：US06432797B1
公开(公告)日：2002-08-13
申请号：US09768487
申请日：2001-01-25
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
IPC分类号： H01L2176
CPC分类号： H01L21/76237 , H01L21/31053 , H01L21/31055
摘要： A method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. Nitrogen atoms are implanted into the oxide layer overlying the trench. The substrate is annealed whereby a layer of nitrogen-rich oxide is formed at the surface of the oxide layer overlying the trench. The oxide layer is planarized to the semiconductor substrate wherein the nitrogen-rich oxide layer is planarized more slowly than the oxide layer resulting in a portion of the oxide layer remaining overlying the trench after the oxide layer overlying the semiconductor substrate has been removed wherein the portion of the oxide layer remaining provides a smooth transition between the shallow trench isolation and the active areas completing the formation of shallow trench isolation in the fabrication of an integrated circuit device.
摘要翻译：描述了形成浅沟槽隔离的方法，其中在隔离和有源区的边缘处的氧化物凹陷被减少或消除。将沟槽蚀刻到半导体衬底中。沉积在半导体衬底上并填充沟槽的氧化物层。将氮原子注入到覆盖沟槽的氧化物层中。将衬底退火，由此在覆盖沟槽的氧化物层的表面上形成一层富氮氧化物。氧化物层平坦化到半导体衬底，其中富氧氧化物层平坦化比氧化物层缓慢，导致一部分氧化物层保留在沟槽上方，在氧化物层覆盖半导体衬底之后，其中部分剩余的氧化物层在浅沟槽隔离和有源区域之间提供平滑的过渡，从而在集成电路器件的制造中完成浅沟槽隔离的形成。

14. 发明授权

US06387747B1 Method to fabricate RF inductors with minimum area 有权
标题翻译：制造面积最小的射频电感器的方法
公开(公告)号：US06387747B1
公开(公告)日：2002-05-14
申请号：US09867561
申请日：2001-05-31
申请人： Randall Cha , Tae Jong Lee , Alex See , Lap Chan , Chua Chee Tee
发明人： Randall Cha , Tae Jong Lee , Alex See , Lap Chan , Chua Chee Tee
IPC分类号： H01L218244
CPC分类号： H01L28/10 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for forming an RF inductor of helical shape having high Q and minimum area. The inductor is fabricated of metal or damascened linear segments formed on three levels of intermetal dielectric layers and interconnected by metal filled vias to form the complete helical shape with electrical continuity.
摘要翻译：一种形成具有高Q值和最小面积的螺旋形RF电感器的方法。电感器由形成在三层金属间电介质层上并由金属填充的通孔相互连接形成具有电连续性的完整螺旋形状的金属或镶嵌的线性段制成。

15. 发明授权

US06355563B1 Versatile copper-wiring layout design with low-k dielectric integration 失效
标题翻译：多功能铜线布局设计，低k电介质集成
公开(公告)号：US06355563B1
公开(公告)日：2002-03-12
申请号：US09798652
申请日：2001-03-05
申请人： Randall Cher Liang Cha , Alex See , Yeow Kheng Lim , Tae Jong Lee , Lap Chan
发明人： Randall Cher Liang Cha , Alex See , Yeow Kheng Lim , Tae Jong Lee , Lap Chan
IPC分类号： H01L2144
CPC分类号： H01L21/76802 , H01L21/76825 , H01L21/76831 , H01L21/76832
摘要： A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.
摘要翻译：描述了一种将低介电常数电介质材料与铜金属化相结合的方法。金属线设置在半导体衬底上并且在其上具有氮化物覆盖层。多晶硅层沉积在氮化物层上并被图案化以形成虚拟通孔。电介质衬垫层共形沉积在氮化物层和虚拟通孔之上。将具有低介电常数的介电层旋涂在衬层上并覆盖虚拟通孔。抛光电介质层，从而暴露虚拟通孔。此后，电介质层被固化，由此形成交联表面层。去除虚设通孔，从而将通孔的一部分氮化物层露出。去除暴露的氮化物层。通孔开口填充有铜层，该铜层在集成电路器件的制造中被平坦化以完成铜金属化。

16. 发明授权

US06348385B1 Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant 有权
标题翻译：使用具有低介电常数的原位掺杂间隔物的具有小覆盖电容的短沟道CMOS晶体管的方法
公开(公告)号：US06348385B1
公开(公告)日：2002-02-19
申请号：US09726256
申请日：2000-11-30
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Chee Tee Chua
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Chee Tee Chua
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/2255 , H01L21/28167 , H01L29/4983 , H01L29/51 , H01L29/66537 , H01L29/66553 , H01L29/7834
摘要： The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.
摘要翻译：使用具有降低结电容的掺杂低K电介质间隔物的替代栅极工艺的晶体管的方法。在基板上形成虚拟栅极。使用伪栅极作为注入掩模将离子注入到衬底中以形成源区和漏区。在源极和漏极区上的衬底上形成掩模层。我们删除虚拟门。在掩蔽层的侧壁上形成掺杂的低k间隔物。掺杂的间隔物被加热以将掺杂剂扩散到衬底中以形成轻掺杂漏极（LDD区）。我们在掩模层上形成一个高k栅介质层。在高K电介质层上形成栅极层。栅极层是化学机械抛光（CMP），以在高k电介质层上形成栅极，并且去除掩模层上的栅极层。

17. 发明申请

US20060040491A1 Slot designs in wide metal lines 有权
标题翻译：狭槽金属线槽设计
公开(公告)号：US20060040491A1
公开(公告)日：2006-02-23
申请号：US10923123
申请日：2004-08-21
申请人： Yeow Lim , Alex See , Tae Lee , David Vigar , Liang Hsia , Kin Pey
发明人： Yeow Lim , Alex See , Tae Lee , David Vigar , Liang Hsia , Kin Pey
IPC分类号： H01L21/4763
CPC分类号： H01L23/528 , H01L21/0276 , H01L21/288 , H01L21/3212 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/7685 , H01L21/76879 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.
摘要翻译：用于宽线槽以减少压力的方法和结构。一种示例性实施例的方法和结构是一种互连结构，包括：包括宽线的互连。宽线有第一个插槽。第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。通孔插头可以从上方或下方接触宽线。另一个示例性实施例是双镶嵌互连结构，包括：双镶嵌形互连件，其包括通孔塞，第一槽和宽线。宽线有第一个插槽。第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。

18. 发明申请

US20050156269A1 Method and apparatus for performing nickel salicidation 有权
公开(公告)号：US20050156269A1
公开(公告)日：2005-07-21
申请号：US11081908
申请日：2005-03-15
申请人： Pooi Lee , Kin Pey , Alex See , Lap Chan
发明人： Pooi Lee , Kin Pey , Alex See , Lap Chan
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L29/49 , H01L27/095
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L29/4933
摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

19. 发明授权

US06680239B1 Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant 失效
标题翻译：有效的隔离与高纵横比浅沟槽隔离和氧或野外植入
公开(公告)号：US06680239B1
公开(公告)日：2004-01-20
申请号：US09624025
申请日：2000-07-24
申请人： Cher Liang Cha , Kok Keng Ong , Alex See , Lap Chan
发明人： Cher Liang Cha , Kok Keng Ong , Alex See , Lap Chan
IPC分类号： H01L2176
CPC分类号： H01L21/76237
摘要： A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effects. In addition, it yields uniform depth trenches while avoiding problems of etch residue at the bottom of the trench. This method is achieved by using a process where a trench is etched, and an oxide layer grown along the bottom and sidewalls of the trench. Oxygen or field isolation ions are then implanted into the bottom of the trench. A nitride spacer is then formed along the bottom and sidewalls of the trench, followed by an isotropic etch removing the nitride and oxide from the bottom of the trench. An oxide deposition then fills the trench, followed by a planarization step completing the isolation structure.
摘要翻译：给出了一种形成具有较高纵横比的浅沟槽隔离（STI）的方法。该方法允许形成更窄和更深的沟槽隔离区域，同时避免由于过度蚀刻和严重的微负载效应引起的基板损伤。此外，它产生均匀的深度沟槽，同时避免沟槽底部的蚀刻残留问题。该方法通过使用其中蚀刻沟槽的工艺和沿着沟槽的底部和侧壁生长的氧化物层来实现。然后将氧或场隔离离子注入到沟槽的底部。然后沿着沟槽的底部和侧壁形成氮化物间隔物，随后通过各向同性蚀刻从沟槽的底部去除氮化物和氧化物。氧化物沉积然后填充沟槽，随后是完成隔离结构的平坦化步骤。

20. 发明授权

US06624489B2 Formation of silicided shallow junctions using implant through metal technology and laser annealing process 有权
公开(公告)号：US06624489B2
公开(公告)日：2003-09-23
申请号：US10033284
申请日：2001-12-31
申请人： Yung Fu Chong , Kin Leong Pey , Alex See
发明人： Yung Fu Chong , Kin Leong Pey , Alex See
IPC分类号： H01L2976
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/2652 , H01L21/268 , H01L21/28052 , H01L29/665
摘要： A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

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