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11. 发明授权

US07508252B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07508252B2
公开(公告)日：2009-03-24
申请号：US11504675
申请日：2006-08-16
申请人： Masafumi Yamazaki , Toshiya Uchida
发明人： Masafumi Yamazaki , Toshiya Uchida
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C11/4074 , G11C5/14 , G11C5/145 , G11C8/08 , G11C11/4072 , G11C11/4085 , H02M3/07 , H02M2001/009
摘要： A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.
摘要翻译：半导体集成电路装置具有产生升压电压的升压电源电路，利用升压电压驱动的内部电路，以及通过接收升压电压来控制内部电路的控制电路。升压电源电路具有用于内部电路的第一输出端子和用于控制电路的第二输出端子。不管从第一端子输出的升压电压的变化如何，来自第二端子的升压电压都具有指定电平。

12. 发明授权

US07221574B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07221574B2
公开(公告)日：2007-05-22
申请号：US11103551
申请日：2005-04-12
申请人： Hiroyoshi Tomita , Toshiya Uchida
发明人： Hiroyoshi Tomita , Toshiya Uchida
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/406 , G11C11/4094 , G11C2207/002 , G11C2207/005 , G11C2211/4065
摘要： A semiconductor storage device has a memory cell (501, 502) storing data; bit lines (BL1, BL2) connected to the memory cell, allowing therethrough data input or output to or from the memory cell; a sense amplifier (506a) connected to said bit lines, amplifying data on the bit lines; and a switching transistor (505a) connecting or disconnecting the bit line connected to the memory cell to or from the bit line connected to the sense amplifier. The switching transistor operates differently in a first memory cell access operation and in a second memory cell access operation.
摘要翻译：半导体存储装置具有存储数据的存储单元（501,502）连接到存储单元的位线（BL 1，BL 2），允许数据输入或输出到存储单元; 连接到所述位线的读出放大器（506a），放大位线上的数据; 以及开关晶体管（505a），连接或断开与连接到读出放大器的位线连接到存储单元的位线。开关晶体管在第一存储器单元存取操作和第二存储单元存取操作中的操作方式不同。

13. 发明授权

US07113027B2 Semiconductor integrated circuit device 有权
公开(公告)号：US07113027B2
公开(公告)日：2006-09-26
申请号：US11104501
申请日：2005-04-13
申请人： Masafumi Yamazaki , Toshiya Uchida
发明人： Masafumi Yamazaki , Toshiya Uchida
IPC分类号： G05F1/10
CPC分类号： G11C11/4074 , G11C5/14 , G11C5/145 , G11C8/08 , G11C11/4072 , G11C11/4085 , H02M3/07 , H02M2001/009
摘要： A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.

14. 发明授权

US06754126B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06754126B2
公开(公告)日：2004-06-22
申请号：US10106597
申请日：2002-03-27
申请人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
发明人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4087 , G11C2211/4061 , G11C2211/4062
摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
摘要翻译：形成多个第一存储块和用于再现第一存储块的数据的第二存储块。当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。因此，可以在不被用户识别的情况下进行刷新操作。即，可以提供用户友好的半导体存储器。

15. 发明授权

US06535452B2 Semiconductor memory device having error correction function for data reading during refresh operation 有权
标题翻译：具有用于刷新操作期间的数据读取的纠错功能的半导体存储器件
公开(公告)号：US06535452B2
公开(公告)日：2003-03-18
申请号：US10097621
申请日：2002-03-15
申请人： Masaki Okuda , Toshiya Uchida
发明人： Masaki Okuda , Toshiya Uchida
IPC分类号： G11C800
CPC分类号： G06F11/1032 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2207/002 , G11C2207/065 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m>1) data pins, each of which continuously receives or outputs n (n>1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, m×n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, m address selection lines which are connected to m respective blocks of the memory blocks corresponding to the m respective data pins, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the m respective blocks and resulting in the n data pieces being input/output to/from the corresponding one of the m respective blocks.
摘要翻译：一种半导体存储器件包括多个存储块，每个存储块彼此独立地刷新，m（m> 1）个数据引脚，每个存储块连续地接收或输出n（n> 1）个数据段，转换电路在并行数据和串行数据之间转换每个数据引脚的数据，相对于每个m个数据引脚并行扩展n个数据段的m×n数据总线，连接到m个相应块的m个地址选择线的对应于各个数据引脚的存储器块，并且同时被激活，将数据总线线路中的任何一个地址选择线激活到相应的m个块中的相应一个，并且导致n个数据段被输入 /输出到相应的m个相应块中的一个。

16. 发明授权

US06529439B2 Semiconductor memory device 有权
公开(公告)号：US06529439B2
公开(公告)日：2003-03-04
申请号：US09789514
申请日：2001-02-22
申请人： Toshiya Uchida , Kota Hara , Shinya Fujioka
发明人： Toshiya Uchida , Kota Hara , Shinya Fujioka
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C5/06
摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

17. 发明授权

US06450877B2 Door mechanism of automotive air conditioning device 有权
标题翻译：汽车空调装置门机构
公开(公告)号：US06450877B2
公开(公告)日：2002-09-17
申请号：US09887005
申请日：2001-06-25
申请人： Akihiro Tsurushima , Takumi Ijichi , Katsuhiro Kurokawa , Toshiya Uchida , Masaharu Onda
发明人： Akihiro Tsurushima , Takumi Ijichi , Katsuhiro Kurokawa , Toshiya Uchida , Masaharu Onda
IPC分类号： B60S154
CPC分类号： B60H1/00857 , B60H1/00692
摘要： A mix door D, which is arranged in a limited space defined between an upstream air passage 10 in which an evaporator 3 is installed and a downstream air passage 11 in which a heater core 4 is installed, is of a sliding type. By guiding a door proper 12 by using a cam groove, a seal member 15 bonded to the door proper 12 is pressed against a contacting member 13 only when the door proper 12 assumes its close position. Smoothed operation of the door proper 12 is achieved with a compact construction of a unit, and sealing and temperature controlling performance is increased.
摘要翻译：设置在设置有蒸发器3的上游空气通道10和安装有加热器芯4的下游空气通道11之间的有限空间中的混合门D是滑动型的。通过使用凸轮槽引导门本体12，仅当门本体12处于其关闭位置时，结合到门本体12的密封构件15被压靠在接触构件13上。门体12的平滑操作通过单元的紧凑结构实现，并且密封和温度控制性能增加。

18. 发明授权

US6104659A Memory device 有权
标题翻译：内存设备
公开(公告)号：US6104659A
公开(公告)日：2000-08-15
申请号：US338599
申请日：1999-06-23
申请人： Yoshimasa Yagishita , Toshiya Uchida , Masaki Okuda
发明人： Yoshimasa Yagishita , Toshiya Uchida , Masaki Okuda
IPC分类号： G11C11/413 , G05F1/00 , G11C5/14 , G11C11/401 , G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C5/143 , G11C5/147
摘要： A memory device comprises: a plurality of banks each of which includes an array of memory cells; and at least a first and a second internal power generator, provided for each of the plurality of banks, for generating an internal power source voltage which differs from a voltage supplied by an external power source. If the internal common power source voltage in the memory device is lower than the first voltage when the power is on, the first and the second internal power generators in a plurality of banks are activated so as to rapidly raise the common internal power source voltage. When the common internal power source voltage in the memory device is higher than the first voltage and lower than the second voltage, the second internal power generators in the banks are activated to compensate for a drop in the internal power source voltage, which is caused by current leakage. When the internal power source voltage in a bank in the activated state is lower than the third voltage, the first and the second internal power generators in the corresponding bank are activated and satisfactorily drive the internal power source voltage in the bank so as to operate the memory device at a high speed.
摘要翻译：存储器件包括：多个存储体，每个存储体包括存储器单元的阵列; 以及为多个组中的每一个提供的至少第一和第二内部发电机，用于产生不同于由外部电源提供的电压的内部电源电压。如果在电源接通时存储器件内部的公共电源电压低于第一电压，则多个组中的第一和第二内部发电机被激活，以便迅速提高公共内部电源电压。当存储器件中的公共内部电源电压高于第一电压并低于第二电压时，该组中的第二内部发电机被激活以补偿内部电源电压的下降，这是由电流泄漏。当处于激活状态的组中的内部电源电压低于第三电压时，相应组中的第一和第二内部发电机被激活并令人满意地驱动组中的内部电源电压，以便操作高速存储设备。

19. 发明授权

US6020612A Semiconductor integrated circuit having efficient layout of wiring lines 失效
标题翻译：具有布线效率高的半导体集成电路
公开(公告)号：US6020612A
公开(公告)日：2000-02-01
申请号：US970563
申请日：1997-11-14
申请人： Takahiro Sawamura , Toshiya Uchida , Hiromi Kanda
发明人： Takahiro Sawamura , Toshiya Uchida , Hiromi Kanda
IPC分类号： H01L21/3205 , H01L21/82 , H01L21/8234 , H01L23/52 , H01L23/522 , H01L27/06 , H01L27/10 , H01L29/76 , H01L31/113
CPC分类号： H01L23/5222 , H01L23/522 , H01L2924/0002 , Y10S257/92
摘要： A semiconductor integrated circuit includes a gate extending in a first direction, a diffusion-layer region corresponding to the gate, and a plurality of backing wiring lines connected to the diffusion-layer region and extending in a first wiring layer in a second direction substantially perpendicular to the first direction. The semiconductor integrated circuit further includes connection wiring lines providing connections between the plurality of backing wiring lines and provided in a second wiring layer.
摘要翻译：半导体集成电路包括：沿第一方向延伸的栅极，对应于栅极的扩散层区域;以及多个背衬布线，其连接到扩散层区域，并沿第二方向基本垂直于第一布线层延伸到第一个方向。半导体集成电路还包括提供多个背衬布线之间的连接并设置在第二布线层中的连接布线。

20. 发明授权

US5995429A Semiconductor memory device capable of multiple word-line selection and method of testing same 失效
标题翻译：能够进行多种字线选择的半导体存储器件及其测试方法
公开(公告)号：US5995429A
公开(公告)日：1999-11-30
申请号：US57403
申请日：1998-04-09
申请人： Kazumi Kojima , Toshiya Uchida , Makoto Yanagisawa
发明人： Kazumi Kojima , Toshiya Uchida , Makoto Yanagisawa
IPC分类号： G11C29/34 , G11C7/00
CPC分类号： G11C29/34
摘要： A semiconductor memory device capable of conducting test operations includes a plurality of word drivers which keep word lines in an active state when the word drivers are selected until the word drivers are reset. The semiconductor memory device further includes a control circuit which successively selects more than one of the plurality of word drivers so as to achieve simultaneous activation of word lines corresponding to selected ones of the plurality of word drivers during the test operations.
摘要翻译：能够进行测试操作的半导体存储器件包括多个字驱动器，当选择字驱动器直到字驱动器复位时，使字线保持在活动状态。半导体存储器件还包括控制电路，其连续地选择多个字驱动器中的多于一个，以便在测试操作期间实现对应于多个字驱动器中的所选字驱动器的字线的同时激活。

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