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11. 发明授权

US4819207A High-speed refreshing rechnique for highly-integrated random-access memory 失效
标题翻译：高集成随机存取存储器的高速刷新特性
公开(公告)号：US4819207A
公开(公告)日：1989-04-04
申请号：US99601
申请日：1987-09-22
申请人： Koji Sakui , Shigeyoshi Watanabe
发明人： Koji Sakui , Shigeyoshi Watanabe
IPC分类号： G11C7/18 , G11C11/4097 , G11C7/00
CPC分类号： G11C11/4097 , G11C7/18
摘要： A divided-bit line type dynamic random-access memory is disclosed which has parallel main bit line pairs in each of which sub-bit line pairs are provided to be electrically parallel with each other. Parallel word lines are provided on the substrate to insulatively cross the sub-bit line pairs. Memory cells are connected to crossing points of the sub-bit line pairs and the word lines. Main sense amplifiers are respectively connected to the main bit line pairs, sub-sense amplifiers are respectively connected to the sub-bit line pairs. A specific refreshing technique is utilized, according to which, when a refreshing operation is executed in a refreshing mode of the memory, the same number of word lines as that of sub-bit line pairs provided in each main-bit line pair are simultaneously selected, and the sub-sense amplifiers are activated to refresh together the memory cells which are connected to the work lines thus selected.
摘要翻译：公开了一种分位线型动态随机存取存储器，其具有并行主位线对，其中每个子位线对被提供为彼此电并联。平行字线设置在衬底上以绝对地穿过子位线对。存储单元连接到子位线对和字线的交叉点。主感测放大器分别连接到主位线对，子读出放大器分别连接到子位线对。使用特定的刷新技术，根据该技术，当在存储器的刷新模式下执行刷新操作时，同时选择与每个主位线对中提供的子位线对相同数量的字线并且子读出放大器被激活以将连接到这样选择的工作线的存储器单元一起刷新。

12. 发明授权

US4798977A Word line driver for use in a semiconductor memory 失效
标题翻译：用于半导体存储器的字线驱动器
公开(公告)号：US4798977A
公开(公告)日：1989-01-17
申请号：US130174
申请日：1987-12-08
申请人： Koji Sakui , Shigeyoshi Watanabe
发明人： Koji Sakui , Shigeyoshi Watanabe
IPC分类号： G11C11/407 , G11C11/408 , H01L21/8242 , H01L27/10 , H01L27/108 , H03K19/017 , H03K19/0175 , H03K19/08 , H03K19/0944 , H03K19/003 , H03K4/58 , H03K17/04 , H03K19/01
CPC分类号： H03K19/01735 , G11C11/4087 , H03K19/01721 , H03K19/09448
摘要： A word line driver for use in a dRAM. This word line driver comprises one npn bipolar transistor and four n-channel transistors. The bipolar transistor is connected between an "H"-level potential terminal and an output terminal. The first MOS transistor is connected in parallel to the bipolar transistor, and is driven by one output signal of a row decoder to supply an output at a sufficiently high "H" level to word lines. The third MOS transistor is coupled between the base and collector of the bipolar transistor, and its gate is connected to the gate of the first MOS transistor. The third MOS transistor supplies a sufficient base current to the base of the bipolar transistor when the word line driver outputs a potential at the "H" level. The second MOS transistor is coupled between the source of the first MOS transistor and a ground potential terminal, and the fourth MOS transistor is coupled between the source of the third MOS transistor and the ground potential terminal. The other output signal, which is complementary to the one output signal of the row decoder, is supplied to the gates of the second and fourth MOS transistors.
摘要翻译：用于dRAM的字线驱动程序。该字线驱动器包括一个npn双极晶体管和四个n沟道晶体管。双极晶体管连接在“H”电平端子和输出端子之间。第一MOS晶体管与双极晶体管并联连接，并由行解码器的一个输出信号驱动，以向字线提供足够高的“H”电平的输出。第三MOS晶体管耦合在双极晶体管的基极和集电极之间，其栅极连接到第一MOS晶体管的栅极。当字线驱动器输出“H”电平的电位时，第三MOS晶体管向双极晶体管的基极提供足够的基极电流。第二MOS晶体管耦合在第一MOS晶体管的源极和地电位端子之间，第四MOS晶体管耦合在第三MOS晶体管的源极和地电位端子之间。与行解码器的一个输出信号互补的另一个输出信号被提供给第二和第四MOS晶体管的栅极。

13. 发明授权

US06295241B1 Dynamic random access memory device 失效
标题翻译：动态随机存取存储器
公开(公告)号：US06295241B1
公开(公告)日：2001-09-25
申请号：US08251649
申请日：1994-05-31
申请人： Shigeyoshi Watanabe , Tsuneaki Fuse , Koji Sakui , Masako Ohta , Yukihito Oowaki , Kenji Numata , Fujio Masuoka
发明人： Shigeyoshi Watanabe , Tsuneaki Fuse , Koji Sakui , Masako Ohta , Yukihito Oowaki , Kenji Numata , Fujio Masuoka
IPC分类号： G11C702
CPC分类号： G11C11/4091 , G11C7/062 , G11C7/14 , G11C11/4099
摘要： Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors.
摘要翻译：这里公开了具有高集成度密度的动态半导体存储器，其具有在基板上形成的并行字线和并行位线。位线包括一对位线。存储器单元耦合到字线和位线对的一个位线。存储单元由亚微米尺寸的MOSFET组成。读出放大器部分连接到一对位线，并且在数据读出模式下感测和放大一对位线之间的电位差。放大器部分具有BIMOS结构，具有MOSFET和双极晶体管。它具有由双极晶体管组成的驱动器部分。

14. 发明授权

US06292390B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06292390B1
公开(公告)日：2001-09-18
申请号：US09755143
申请日：2001-01-08
申请人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
发明人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
IPC分类号： G11C1134
CPC分类号： H01L27/1025 , G11C11/39 , H01L29/36 , H01L29/42304 , H01L29/456 , H01L29/73 , H01L29/7322 , H01L29/885 , H03F3/04 , H03K3/021 , H03K17/567
摘要： A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE
摘要翻译：半导体器件包括双极晶体管，其发射极 - 集电极电压被设置为满足条件IBE

15. 发明授权

US5892724A NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines 失效
标题翻译： NAND型动态RAM具有耦合到多开位线的临时存储寄存器和读出放大器
公开(公告)号：US5892724A
公开(公告)日：1999-04-06
申请号：US848152
申请日：1997-04-29
申请人： Takehiro Hasegawa , Yukihito Oowaki , Fujio Masuoka , Ryu Ogiwara , Shinichiro Shiratake , Shigeyoshi Watanabe
发明人： Takehiro Hasegawa , Yukihito Oowaki , Fujio Masuoka , Ryu Ogiwara , Shinichiro Shiratake , Shigeyoshi Watanabe
IPC分类号： G11C7/10 , G11C11/404 , G11C11/4096 , G11C11/4097 , G11C8/00
CPC分类号： G11C7/106 , G11C11/4045 , G11C11/4096 , G11C11/4097 , G11C7/1051 , G11C7/1078
摘要： A sense amplifier is connected between memory cell arrays, a re-writing register is arranged adjacent to the sense amplifier, first transfer gates are disposed between the sense amplifier and the memory cell arrays, second transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.
摘要翻译：读出放大器连接在存储单元阵列之间，重写寄存器与读出放大器相邻地布置，第一传输门设置在读出放大器和存储单元阵列之间，第二传输门提供在存储单元的位线之间阵列和全局位线，以及用于控制传输门的栅极控制电路。当读出数据被写入寄存器时，读出放大器的节点与位线和全局位线电分离。

16. 发明授权

US5717625A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5717625A
公开(公告)日：1998-02-10
申请号：US784963
申请日：1997-01-16
申请人： Takehiro Hasegawa , Yukihito Oowaki , Shigeyoshi Watanabe , Ken-ichi Maeda , Mitsuo Saito , Masako Yoshida , Ryo Fukuda , Shinichiro Shiratake
发明人： Takehiro Hasegawa , Yukihito Oowaki , Shigeyoshi Watanabe , Ken-ichi Maeda , Mitsuo Saito , Masako Yoshida , Ryo Fukuda , Shinichiro Shiratake
IPC分类号： G11C8/08 , G11C11/404 , G11C15/00
CPC分类号： G11C8/08 , G11C11/4045
摘要： In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.
摘要翻译：在其中提供通过串联连接多个存储单元而形成的多个存储单元单元的半导体存储器件中，并且每个存储单元单元连接到位线，该半导体存储器件包括用于直接读取数据的数据的控制电路当前一行地址指定与当前行地址相同的存储单元时，读取操作期间的寄存器单元，以及数据改变控制电路，用于将存储单元单元的任意存储单元的数据改变为最靠近的存储单元的数据存储单元单元中的位线接触，以及用于选择存储单元单元的存储器的相应行地址的行解码器，比存储单元单元中选择存储单元的行地址的部分高。

17. 发明授权

US4831433A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4831433A
公开(公告)日：1989-05-16
申请号：US226532
申请日：1988-07-27
申请人： Mitsugi Oguara , Fumio Horiguchi , Shigeyoshi Watanabe
发明人： Mitsugi Oguara , Fumio Horiguchi , Shigeyoshi Watanabe
IPC分类号： H01L21/822 , H01L23/485 , H01L27/02 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L24/06 , H01L27/0207 , H01L27/108 , H01L2224/05554 , H01L2224/48247 , H01L2224/49171 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/19041 , H01L2924/30105
摘要： A semiconductor device includes a rectangular semiconductor chip, first to fourth memory cell arrays formed on the semiconductor chip, and first to fourth bonding pads formed on the peripheral part of the semiconductor chip. In this semiconductor device in particular, first bonding pads are disposed along a first long side of the semiconductor chip while second bonding pads are disposed along a second long side of the chip. The first and second memory cell arrays are disposed between the first bonding pads and the second long side while the third and fourth memory cell arrays are disposed between the first long side and the second pads.
摘要翻译：半导体器件包括矩形半导体芯片，形成在半导体芯片上的第一至第四存储单元阵列以及形成在半导体芯片周边部分上的第一至第四焊盘。特别地，在该半导体器件中，沿着半导体芯片的第一长边设置第一接合焊盘，而沿芯片的第二长边设置第二接合焊盘。第一和第二存储单元阵列设置在第一接合焊盘和第二长边之间，而第三和第四存储单元阵列设置在第一长边和第二焊盘之间。

18. 发明授权

US4800530A Semiconductor memory system with dynamic random access memory cells 失效
标题翻译：具有动态随机存取存储单元的半导体存储器系统
公开(公告)号：US4800530A
公开(公告)日：1989-01-24
申请号：US85086
申请日：1987-08-13
申请人： Yasuo Itoh , Fumio Horiguchi , Shigeyoshi Watanabe , Kazunori Ohuchi , Mitsugi Ogura
发明人： Yasuo Itoh , Fumio Horiguchi , Shigeyoshi Watanabe , Kazunori Ohuchi , Mitsugi Ogura
IPC分类号： G11C11/40 , G11C7/00 , G11C7/10 , G11C7/22
CPC分类号： G11C7/22 , G11C7/00 , G11C7/1033
摘要： A dynamic random access memory system comprises first and second memory banks. A plurality of memory cells connected to a word line are grouped into first and second groups. The first group is arranged in the first memory bank and the second group is arranged in the second memory bank. Read/write means is provided in which each n bits from and to the first group and each n bits from and to the second group are read and written alternatively. Each bit is read and written in synchronism with the toggles of a column address strobe signal.
摘要翻译：动态随机存取存储器系统包括第一和第二存储体。连接到字线的多个存储单元被分组为第一组和第二组。第一组布置在第一存储体中，第二组布置在第二存储体中。提供读/写装置，其中从第一组的每个n位和从第二组的每个n位和第二组的每个n位被交替地读取和写入。每个位与列地址选通信号的切换同步读写。

19. 发明授权

US08204670B2 Cruise control system using instruction sent from switch 有权
标题翻译：巡航控制系统使用从开关发出的指令
公开(公告)号：US08204670B2
公开(公告)日：2012-06-19
申请号：US11882291
申请日：2007-07-31
申请人： Shigeyoshi Watanabe
发明人： Shigeyoshi Watanabe
IPC分类号： G06F7/00
CPC分类号： B60W10/06 , B60W10/11
摘要： In a cruise control system installed in a vehicle and electrically connected to a plurality of switches installed therein, a detecting unit detects that one of the plurality of switches is operated. A cruise control unit executes cruise control of the vehicle based on an instruction corresponding to the one of the plurality of switches upon detection of the one of the plurality of switches being operated. When the detecting unit detects that, during the first switch being operated, the second switch is operated, and when a combination of first and second instructions sent from the detected first and second switches is matched with at least one predetermined combination of instructions to be sent from the plurality of switches, a cruise control disabling unit disables the cruise control unit to execute cruise control of the vehicle based on the second instruction.
摘要翻译：在安装在车辆中的电气连接到安装在其中的多个开关的巡航控制系统中，检测单元检测到多个开关中的一个开关被操作。在检测到所述多个开关中的一个开关被操作时，巡航控制单元基于与所述多个开关中的一个开关相对应的指令来执行车辆的巡航控制。当检测单元检测到在操作的第一开关期间操作第二开关，并且当从检测到的第一和第二开关发送的第一和第二指令的组合与要发送的指令的至少一个预定组合匹配时巡航控制禁止单元从多个开关中，基于第二指令使巡航控制单元不执行车辆的巡航控制。

20. 发明授权

US5732010A Dynamic random access memory device with the combined open/folded bit-line pair arrangement 失效
标题翻译：具有组合打开/折叠位线对布置的动态随机存取存储器件
公开(公告)号：US5732010A
公开(公告)日：1998-03-24
申请号：US771434
申请日：1996-12-20
申请人： Daisaburo Takashima , Shigeyoshi Watanabe
发明人： Daisaburo Takashima , Shigeyoshi Watanabe
IPC分类号： G11C7/18 , G11C11/4097 , H01L27/108 , G11C11/401
CPC分类号： H01L27/10805 , G11C11/4097 , G11C7/18
摘要： A semiconductor memory device of the present invention comprises a plurality of word lines formed on a substrate, a plurality of bit lines perpendicular to the word lines and divided into bit-line groups in the column direction along the word line, each group containing three bit lines, and arrays of memory cells arranged at the intersections of word lines and bit lines, wherein two memory cells are placed at two of every three adjacent intersections arranged in each of the row and column directions, and where these memory cell arrays are divided into subarrays in the row direction, each of the cell arrays is divided into cell blocks in the row direction, two of the three bit lines in each bit-line group along the bit line are crossed each other between adjacent cell blocks, and a plurality of sense amplifiers are placed between adjacent cell arrays so as to correspond to cell blocks.
摘要翻译：本发明的半导体存储器件包括形成在基板上的多条字线，与字线垂直的多个位线，沿着字线在列方向上分成位线组，每组包含三位线和排列在字线和位线的交点处的存储器单元阵列，其中两个存储单元被放置在布置在行和列方向中的每一个中的每三个相邻交点中的两个处，并且其中这些存储单元阵列被分成在行方向上的子阵列中，每个单元阵列被划分为行方向上的单元块，沿位线的每个位线组中的三个位线中的两个在相邻单元块之间彼此交叉，并且多个感测放大器被放置在相邻单元阵列之间，以便对应于单元块。

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