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11. 发明授权

US06498524B1 Input/output data synchronizing device 有权
标题翻译：输入/输出数据同步装置
公开(公告)号：US06498524B1
公开(公告)日：2002-12-24
申请号：US09706731
申请日：2000-11-07
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： H03L708
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

12. 发明授权

US06403048B1 Combustion catalysts and processes for removing organic compounds 有权
标题翻译：燃烧催化剂和除去有机化合物的方法
公开(公告)号：US06403048B1
公开(公告)日：2002-06-11
申请号：US09471001
申请日：1999-12-23
申请人： Wataru Kobayashi , Masao Nakano
发明人： Wataru Kobayashi , Masao Nakano
IPC分类号： B01J800
CPC分类号： B01J21/066 , B01D53/8662 , B01D53/8668 , B01J21/06 , B01J21/063 , B01J23/42 , B01J29/068 , B01J29/18 , B01J29/40 , B01J29/7007 , B01J35/0006 , B01J35/10 , B01J35/1085 , B01J2229/20
摘要： Catalysts for removing organic compounds from a gas stream containing the same and processes for removing organic compounds from the gas stream using the cataylst are disclosed. According to the first aspect, a combustion catalyst for removing organic compounds comprises a mixture of a zeolite and a metal oxide containing at least one of the elements of the platinum group. According to the second aspect, a combustion catalyst for removing organic compounds comprises an alumina having such a pore size distribution that, where “a” represents a pore radius in Å at the maximum of the pore size distribution curve, the accumlated pore volume of pores having radii in the range of “a”±Å is at least 65% of the total volume of all the pores, said alumina containing less than 1% by weight of rare earth elements and being loaded with one or more elements of the platinum group. According to third aspect, there is a process for removing organic compounds, said process comprising the step of contacting organic compounds with either one of the catalysts according to the first and second aspects of the invention.
摘要翻译：公开了从含有该有机化合物的气流中除去有机化合物的催化剂和使用催化剂从气流中除去有机化合物的方法。根据第一方面，用于除去有机化合物的燃烧催化剂包括沸石和金属的混合物含有铂族元素中的至少一种元素的氧化物。根据第二方面，用于除去有机化合物的燃烧催化剂包括具有孔尺寸分布的氧化铝，其中“a”表示孔径分布曲线最大值处的孔半径，孔的累积孔体积具有在“a”的范围内的半径为所有孔的总体积的至少65％，所述氧化铝含有少于1重量％的稀土元素并且装载有一种或多种铂族元素根据第三方面，有一种除去有机化合物的方法，所述方法包括使有机化合物与根据本发明的第一和第二方面的任一种催化剂接触的步骤。

13. 发明授权

US06323150B1 Process for preparing solid titanium catalyst component, olefin polymerization catalyst, and olefin polymerization process 有权
标题翻译：固体钛催化剂组分，烯烃聚合催化剂和烯烃聚合方法的制备方法
公开(公告)号：US06323150B1
公开(公告)日：2001-11-27
申请号：US09131837
申请日：1998-08-10
申请人： Shinichi Kojoh , Tsuneo Yashiki , Kazumitsu Kawakita , Masao Nakano , Sadahiko Matsuura
发明人： Shinichi Kojoh , Tsuneo Yashiki , Kazumitsu Kawakita , Masao Nakano , Sadahiko Matsuura
IPC分类号： B01J3100
CPC分类号： C08F10/00 , C08F4/651 , C08F4/6543
摘要： Disclosed is a process for preparing a solid titanium catalyst component, comprising the steps of (I) contacting a liquid magnesium compound with a liquid titanium compound to precipitate a solid in the contact liquid (&bgr;), and adding an electron donor (d-i) selected from the group consisting of a polycarboxylic ester and a polyether compound to the contact liquid (&bgr;) during the time from beginning to end of the solid precipitation, to form a solid product (&agr;); and (II) contacting the solid product (&agr;) obtained after completion of the solid precipitation with an electron donor (d-ii) selected from the group consisting of a polycarboxylic ester and a polyether compound, to prepare a solid titanium catalyst component. According to the process, a solid titanium catalyst component capable of polymerizing an olefin with high activity and capable of preparing an olefin polymer of high stereoregularity can be prepared. Also disclosed are an olefin polymerization catalyst containing a solid titanium catalyst component obtained by the above process and an olefin polymerization process using the olefin polymerization catalyst.
摘要翻译：公开了一种制备固体钛催化剂组分的方法，包括以下步骤：（I）使液体镁化合物与液体钛化合物接触以沉淀接触液体中的固体（β），并加入选择的电子给体（di）从固体沉淀开始到结束的时间期间由聚羧酸酯和聚醚化合物组成接触液（β），形成固体产物（α）; 和（II）使固体沉淀完成后得到的固体产物（α）与选自多羧酸酯和聚醚化合物的电子给体（d-ii）接触，制备固体钛催化剂组分。根据该方法，可以制备能够使活性高的烯烃聚合并能够制备具有高立构规整性的烯烃聚合物的固体钛催化剂组分。还公开了含有通过上述方法获得的固体钛催化剂组分和使用烯烃聚合催化剂的烯烃聚合方法的烯烃聚合催化剂。

14. 发明授权

US06298004B1 Semiconductor device, semiconductor system, and digital delay circuit 失效
标题翻译：半导体器件，半导体系统和数字延迟电路
公开(公告)号：US06298004B1
公开(公告)日：2001-10-02
申请号：US08892790
申请日：1997-07-15
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： G11C800
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

15. 发明授权

US5266636A Process for producing polypropylene and stretched polypropylene film 失效
标题翻译：生产聚丙烯和拉伸聚丙烯薄膜的方法
公开(公告)号：US5266636A
公开(公告)日：1993-11-30
申请号：US928015
申请日：1992-08-11
申请人： Mamoru Kioka , Masaya Yamada , Masanobu Ishiyama , Masao Nakano , Akinori Toyota
发明人： Mamoru Kioka , Masaya Yamada , Masanobu Ishiyama , Masao Nakano , Akinori Toyota
IPC分类号： C08F10/06 , C08L23/10 , C08F297/08 , C08J5/18 , C08L23/20
CPC分类号： C08F10/06
摘要： A process for producing polypropylene, which comprises preliminarily polymerizing 3-methylbutene-1 in the presence of a catalyst system formed from[A] a solid titanium catalyst component containing magnesium, titanium, halogen and polycarboxylic acid esters as essential components,[B] an organoaluminum compound, and[C] an organosilicon compound represented by the general formula R.sub.n Si(OR').sub.4-n wherein R and R' represent a hydrocarbon group, and 0
摘要翻译：一种生产聚丙烯的方法，其包括在由[A]含有镁，钛，卤素和多元羧酸酯作为必要组分的固体钛催化剂组分形成的催化剂体系的情况下预先聚合3-甲基丁烯[B] 有机铝化合物和[C]由通式RnSi（OR'）4-n表示的有机硅化合物，其中R和R'表示烃基，0

16. 发明授权

US5253204A Semiconductor memory device having a boost circuit 失效
标题翻译：具有升压电路的半导体存储器件
公开(公告)号：US5253204A
公开(公告)日：1993-10-12
申请号：US747049
申请日：1991-08-19
申请人： Atsushi Hatakeyama , Masao Nakano
发明人： Atsushi Hatakeyama , Masao Nakano
IPC分类号： G11C11/407 , G11C8/08 , G11C11/408
CPC分类号： G11C8/08 , G11C11/4085
摘要： A semiconductor memory device comprises a memory cell array including a plurality of memory cells, a word line selection circuit for selecting a word line, a bit line selection circuit for selecting a bit line, an input/output circuit for supplying data to be written to a selected memory cell via the selected bit line and for reading data from the selected memory cell via the selected bit line, a word line driver including a MOS transistor having a drain supplied with a supply voltage and a source connected to the word line selection circuit for supplying a word line voltage to the selected word line via the word line selection circuit, a word line boosting circuit connected to the drain of the MOS transistor for boosting the word line voltage via the MOS transistor, a boosting capacitor connected across the source and the gate of the MOS transistor, and a clamping circuit connected to the gate of said MOS transistor for clamping the voltage level at a predetermined level.

17. 发明授权

US5001289A Shaped zeolite catalyst for liquid phase organic reactions 失效
标题翻译：用于液相有机反应的成型沸石催化剂
公开(公告)号：US5001289A
公开(公告)日：1991-03-19
申请号：US384050
申请日：1989-07-24
申请人： Masao Nakano , Kazuhiko Sekizawa , Toshio Hironaka , Kiyotaka Oyama , Seiichi Asano
发明人： Masao Nakano , Kazuhiko Sekizawa , Toshio Hironaka , Kiyotaka Oyama , Seiichi Asano
IPC分类号： B01J29/06 , B01J29/08 , B01J29/50 , B01J29/60 , C07B39/00 , C07B61/00 , C07C17/00 , C07C17/12 , C07C25/02 , C07C67/00 , C10G35/10
CPC分类号： B01J29/084 , B01J29/60 , C07B39/00 , C07C17/12 , C10G35/10 , B01J2229/40
摘要： Disclosed is a shaped zeolite catalyst used for liquid phase organic reactions. The shaped zeolite catalyst is composed of substantially spherical particles having a particle diameter substantially in the range of from 70 to 300 .mu.m, and which has fine pores having a pore volume of 0.4 to 1 cc per gram of the shaped catalyst and a median pore diameter based on the pore volume of 1,000 to 5,500 .ANG..

18. 发明授权

US4914247A Process for preparing para-substituted halogenobenzene derivatives 失效
标题翻译：制备对位取代的卤代苯衍生物的方法
公开(公告)号：US4914247A
公开(公告)日：1990-04-03
申请号：US374578
申请日：1989-06-30
申请人： Kazuhiko Sekizawa , Toshio Hironaka , Masao Nakano , Yukihiro Tsutsumi
发明人： Kazuhiko Sekizawa , Toshio Hironaka , Masao Nakano , Yukihiro Tsutsumi
IPC分类号： B01J29/00 , B01J29/60 , B01J29/70 , C07B61/00 , C07C17/00 , C07C17/10 , C07C17/12 , C07C25/02 , C07C25/08 , C07C67/00
CPC分类号： B01J29/60 , C07C17/12
摘要： A para-substituted halogenobenzene derivative is prepared by halogenating a benzene derivative in the liquid phase in the presence of a molded zeolite catalyst body comprising, based on the weight of the molded zeolite catalyst body, 10 to 95% by weight of an L-type zeolite as the anhydrous state and 5 to 90% by weight of amorphous silica.
摘要翻译：对位取代的卤代苯衍生物是通过在模压的沸石催化剂体的存在下，将液体中的苯衍生物卤化来制备的，所述沸石催化剂体系基于模制的沸石催化剂体的重量为10至95重量％的L型沸石为无水状态，5〜90重量％的无定形二氧化硅。

19. 发明授权

US4870617A Semiconductor memory device having data bus reset circuits 失效
标题翻译：半导体存储器件具有数据总线复位电路
公开(公告)号：US4870617A
公开(公告)日：1989-09-26
申请号：US97558
申请日：1987-09-16
申请人： Masao Nakano , Tsuyoshi Ohira , Hirohiko Mochizuki , Yukinori Kodama , Hidenori Nomura
发明人： Masao Nakano , Tsuyoshi Ohira , Hirohiko Mochizuki , Yukinori Kodama , Hidenori Nomura
IPC分类号： G11C11/409 , G11C5/06 , G11C7/10 , G11C11/401
CPC分类号： G11C5/063 , G11C7/1048
摘要： A semiconductor memory device comprises a plurality of reset circuits connected to a data bus pair at different locations. Before each read operation, the reset circuits reset the data bus pair to a predetermined reset voltage. The resetting of the data bus pair is virtually unaffected by the distributed resistances and parasitic capacitances of the data bus pair, since the resetting is carried out at a plurality of locations on the data bus pair.
摘要翻译：半导体存储器件包括在不同位置连接到数据总线对的多个复位电路。在每次读取操作之前，复位电路将数据总线对复位到预定的复位电压。数据总线对的复位实际上不受数据总线对的分布电阻和寄生电容的影响，因为复位是在数据总线对上的多个位置进行的。

20. 发明授权

US4740926A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4740926A
公开(公告)日：1988-04-26
申请号：US843356
申请日：1986-03-24
申请人： Yoshihiro Takemae , Masao Nakano , Kimiaki Sato , Nobumi Kodama
发明人： Yoshihiro Takemae , Masao Nakano , Kimiaki Sato , Nobumi Kodama
IPC分类号： G11C11/409 , G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094 , G11C11/4091
摘要： A semiconductor memory device comprises a memory cell array, a bit line charge-up circuit coupled to one of a plurality of pairs of bit lines from the memory cell array for initially charging up the one pair of bit lines to a first voltage which is lower than a power source voltage used to drive the semiconductor memory device, an active restore circuit coupled to the one pair of bit lines and a switching circuit coupled to the one pair of bit lines for disconnecting the one pair of bit lines into a first pair of bit line sections on the side of the memory cell array and a second pair of bit line sections on the side of the active restore circuit after the one pair of bit lines are initially charged up to the first voltage. The active restore circuit charges up one of the pair of bit line sections on the side of the active restore circuit to a second voltage which is higher than the first voltage depending on a datum read out from the memory cell array.
摘要翻译：半导体存储器件包括存储单元阵列，位线充电电路，其耦合到存储单元阵列的多对位线中的一对，用于将一对位线初始充电至较低的第一电压比用于驱动半导体存储器件的电源电压，耦合到一对位线的有效恢复电路和耦合到该一对位线的开关电路，用于将一对位线断开为第一对位在存储单元阵列一侧的位线部分和在一对位线开始被充电至第一电压之后的有效恢复电路侧的第二对位线部分。有源恢复电路根据从存储单元阵列读出的数据，将有源恢复电路一侧的一对位线部分中的一个充电到高于第一电压的第二电压。

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