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11. 发明申请

US20080116483A1 HIGH-QUALITY SGOI BY ANNEALING NEAR THE ALLOY MELTING POINT 失效
标题翻译：高品质SGOI通过靠近合金熔点来退火
公开(公告)号：US20080116483A1
公开(公告)日：2008-05-22
申请号：US12027561
申请日：2008-02-07
申请人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Richard Murphy , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Richard Murphy , Devendra Sadana
IPC分类号： H01L29/165
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓形成堆垛层错缺陷。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

12. 发明申请

US20080057684A1 METHOD FOR FABRICATING LOW-DEFECT-DENSITY CHANGED ORIENTATION Si 失效
标题翻译：用于制造低密度变化方位的方法Si
公开(公告)号：US20080057684A1
公开(公告)日：2008-03-06
申请号：US11873928
申请日：2007-10-17
申请人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
发明人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/2022
摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.
摘要翻译：本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向具有不同的方向。更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶非晶层的原始方向。本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

13. 发明申请

US20060057403A1 Use of thin SOI to inhibit relaxation of SiGe layers 审中-公开
公开(公告)号：US20060057403A1
公开(公告)日：2006-03-16
申请号：US11268096
申请日：2005-11-07
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
IPC分类号： B32B13/04 , B32B15/04 , B32B9/00
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

14. 发明申请

US20060042542A1 Method of producing silicon-germanium-on-insulator material using unstrained Ge-containing source layers 有权
公开(公告)号：US20060042542A1
公开(公告)日：2006-03-02
申请号：US10932598
申请日：2004-09-02
申请人： Stephen Bedell , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Keith Fogel , Devendra Sadana
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： H01L21/76254
摘要： A method of fabricating a high-quality relaxed SiGe-on-insulator substrate material is provided in which a prefabricated silicon-on-insulator substrate is first exposed to an unstrained Ge-containing source and then heated (annealed/oxidized) to cause Ge diffusion and thermal mixing of Ge within a single-crystal Si-containing layer of the prefabricated silicon-on-insulator substrate. The unstrained Ge-containing source can comprise a solid Ge-containing source, a gaseous Ge-containing source, or ions of Ge.

15. 发明申请

US20050208780A1 High-quality SGOI by oxidation near the alloy melting temperature 有权
标题翻译：高品质的SGOI通过氧化在合金熔化温度附近
公开(公告)号：US20050208780A1
公开(公告)日：2005-09-22
申请号：US11029921
申请日：2005-01-05
申请人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： C30B1/00 , H01L21/00 , H01L21/20 , H01L21/324 , H01L21/477 , H01L21/762 , H01L27/01
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。

16. 发明申请

US20050130424A1 Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion 有权
标题翻译：使用氢气注入来改善由热扩散制成的绝缘体上硅材料的材料特性
公开(公告)号：US20050130424A1
公开(公告)日：2005-06-16
申请号：US10982411
申请日：2004-11-05
申请人： Stephen Bedell , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Keith Fogel , Devendra Sadana
IPC分类号： H01L29/161 , H01L21/20 , H01L21/265 , H01L21/762 , B32B9/04 , H01L21/302 , H01L21/36 , H01L21/461
CPC分类号： H01L21/76243 , H01L21/02378 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02664 , Y10S438/933
摘要： A method of forming a relaxed SiGe-on-insulator substrate having enhanced relaxation, significantly lower defect density and improved surface quality is provided. The method includes forming a SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an underlying barrier layer that is resistant to Ge diffusion. Next, ions that are capable of forming defects that allow mechanical decoupling at or near said interface are implanted into the structure and thereafter the structure including the implanted ions is subjected to a heating step which permits interdiffusion of Ge throughout the first single crystal Si layer and the SiGe layer to form a substantially relaxed, single crystal and homogeneous SiGe layer atop the barrier layer. SiGe-on-insulator substrates having the improved properties as well as heterostructures containing the same are also provided.
摘要翻译：提供了一种形成松弛的绝缘体上硅衬底的方法，其具有增强的松弛，显着降低缺陷密度和改进的表面质量。该方法包括在第一单晶Si层的表面上形成SiGe合金层。第一单晶硅层具有与Ge扩散耐受的下层阻挡层的界面。接下来，能够形成允许在界面处或附近机械解耦的缺陷的离子被注入到结构中，此后包括注入的离子的结构经受加热步骤，其允许Ge贯穿整个第一单晶Si层和 SiGe层，以形成在阻挡层顶上基本上松弛的单晶和均匀的SiGe层。还提供了具有改进性能的绝缘体上硅衬底以及含有其的异质结构。

17. 发明申请

US20050003626A1 Control of buried oxide in SIMOX 有权
标题翻译：在SIMOX中控制埋氧化物
公开(公告)号：US20050003626A1
公开(公告)日：2005-01-06
申请号：US10896812
申请日：2004-07-22
申请人： Stephen Fox , Neena Garg , Kenneth Giewont , Junedong Lee , Siegfried Maurer , Dan Moy , Maurice Norcott , Devendra Sadana
发明人： Stephen Fox , Neena Garg , Kenneth Giewont , Junedong Lee , Siegfried Maurer , Dan Moy , Maurice Norcott , Devendra Sadana
IPC分类号： H01L21/762 , H01L21/76 , H01L21/425
CPC分类号： H01L21/76243
摘要： A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.
摘要翻译：描述了一种用于形成绝缘体上半导体（SOI）衬底的方法，其包括加热衬底，将氧注入加热衬底，冷却衬底，注入冷却衬底和退火的步骤。植入的步骤可以是几种能量以提供多个深度和相应的埋入损伤区域。在植入之前，可以执行清洁衬底表面和/或在其上形成图案化掩模的步骤。本发明克服了提高掩埋氧化物质量及其性能如表面粗糙度，均匀厚度和击穿电压Vbd的问题。

18. 发明申请

US20070111463A1 STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER 失效
标题翻译：通过阳极氧化P +硅锗层的分级制备的绝缘硅绝缘体
公开(公告)号：US20070111463A1
公开(公告)日：2007-05-17
申请号：US11620663
申请日：2007-01-06
申请人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/337 , H01L27/12 , H01L21/76
CPC分类号： H01L21/76259 , Y10S438/967
摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.
摘要翻译：提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

19. 发明申请

US20060030133A1 Relaxed, low-defect SGOI for strained Si CMOS applications 有权
标题翻译：用于应变Si CMOS应用的轻松，低缺陷SGOI
公开(公告)号：US20060030133A1
公开(公告)日：2006-02-09
申请号：US11208359
申请日：2005-08-19
申请人： Paul Agnello , Stephen Bedell , Robert Dennard , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Paul Agnello , Stephen Bedell , Robert Dennard , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： H01L21/20 , H01L33/00 , H01L21/36
CPC分类号： H01L21/324 , C30B25/02 , C30B29/52 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66893 , H01L29/78603
摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
摘要翻译：提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

20. 发明申请

US20060001089A1 ULTRA-THIN, HIGH QUALITY STRAINED SILICON-ON-INSULATOR FORMED BY ELASTIC STRAIN TRANSFER 失效
标题翻译：超薄薄膜，高品质应变硅橡胶绝缘子，由弹性应变转移
公开(公告)号：US20060001089A1
公开(公告)日：2006-01-05
申请号：US10883883
申请日：2004-07-02
申请人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
发明人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
IPC分类号： H01L31/0392 , H01L21/84
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.
摘要翻译：提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

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