专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5605855A Process for fabricating a graded-channel MOS device 失效
标题翻译：用于制造渐变通道MOS器件的工艺
公开(公告)号：US5605855A
公开(公告)日：1997-02-25
申请号：US395339
申请日：1995-02-28
申请人： Ko-Min Chang , Marius Orlowski , Craig Swift , Shih-Wei Sun , Shiang-Chyong Luo
发明人： Ko-Min Chang , Marius Orlowski , Craig Swift , Shih-Wei Sun , Shiang-Chyong Luo
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L29/10 , H01L21/8234
CPC分类号： H01L29/66583 , H01L21/2652 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/66553
摘要： A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).
摘要翻译：用于制造渐变沟道MOS器件的工艺包括在半导体衬底（10）的表面上形成掩模层（16），并通过栅氧化层（12）从表面分离。使用掩模层（16）作为掺杂掩模，在半导体衬底（10）的沟道区（20）中形成第一掺杂区（22）。第二掺杂区域（24）形成在沟道区域（20）中并且从半导体衬底（10）的主表面（14）延伸到第一掺杂区域（22）。栅极电极（34）形成在掩模层（16）的开口（18）内，并与沟道区域（20）对准。在去除掩模层（16）时，源极和漏极区（36,38）形成在半导体衬底（10）中并与栅电极（34）对齐。

12. 发明申请

US20150349142A1 SPLIT GATE MEMORY CELL WITH IMPROVED ERASE PERFORMANCE 有权
标题翻译：具有改进的擦除性能的分离器门存储器单元
公开(公告)号：US20150349142A1
公开(公告)日：2015-12-03
申请号：US14288975
申请日：2014-05-28
申请人： BRIAN A. WINSTEAD , Ko-Min Chang , Craig T. Swift
发明人： BRIAN A. WINSTEAD , Ko-Min Chang , Craig T. Swift
IPC分类号： H01L29/792 , H01L29/51 , H01L21/28 , G11C16/14
CPC分类号： H01L21/28282 , G11C16/0425 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.
摘要翻译：半导体器件包括半导体衬底，在衬底的一部分上的电荷存储堆叠。电荷存储堆叠包括第一电介质层，与第一介电层接触的纳米晶体层，与纳米晶体层接触并与其接触的第二电介质层，在第二介电层上并与第二介电层接触的氮化物层，以及在氮化物层上的第三电介质层。

13. 发明申请

US20130323922A1 SPLIT GATE MEMORY DEVICE WITH GAP SPACER 有权
公开(公告)号：US20130323922A1
公开(公告)日：2013-12-05
申请号：US13961574
申请日：2013-08-07
申请人： JINMIAO J. SHEN , Ko-Min Chang , Brian A. Winstead
发明人： JINMIAO J. SHEN , Ko-Min Chang , Brian A. Winstead
IPC分类号： H01L29/423
CPC分类号： H01L29/42344 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A method for forming a split gate device includes forming a first sidewall of a first conductive gate layer, wherein the semiconductor layer includes a tunnel region laterally adjacent the first sidewall, forming a dielectric layer along the first sidewall to provide for increased thickness of a gap spacer, forming a charge storage layer over a portion of a top surface of the first conductive layer and over the tunnel region, and forming a second conductive gate layer over the charge storage layer.

14. 发明申请

US20100240156A1 METHOD FOR PROVIDING A NON-VOLATILE MEMORY 有权
标题翻译：提供非易失性存储器的方法
公开(公告)号：US20100240156A1
公开(公告)日：2010-09-23
申请号：US12405308
申请日：2009-03-17
申请人： Mohammed Suhail , Ko-Min Chang , Peter J. Kuhn , Erwin J. Prinz
发明人： Mohammed Suhail , Ko-Min Chang , Peter J. Kuhn , Erwin J. Prinz
IPC分类号： H01L21/66
CPC分类号： G11C29/06 , G11C16/04 , G11C29/50 , G11C29/50004 , G11C29/50016 , G11C2029/0403
摘要： Testing a non volatile memory by exposing the non volatile memory to particle radiation (e.g. xenon ions) to emulate memory cell damage due to data state changing events of a non volatile memory cell. After the exposing, the memory cells are subjected to tests and the results of the tests are used to develop reliability indications of the non volatile memory. Integrated circuits with non volatile memories of the same design are provided. Reliability representations of the integrated circuits can be made with respect to a number of data state charging events based on the exposure and subsequent tests.
摘要翻译：通过将非易失性存储器暴露于粒子辐射（例如氙离子）来测试非易失性存储器，以模拟由非易失性存储器单元的数据状态改变事件引起的存储器单元损坏。在曝光之后，对存储器单元进行测试，并且测试结果用于开发非易失性存储器的可靠性指示。提供了具有相同设计的非易失性存储器的集成电路。集成电路的可靠性表示可以基于曝光和随后的测试相对于多个数据状态充电事件进行。

15. 发明授权

US07700439B2 Silicided nonvolatile memory and method of making same 有权
标题翻译：硅化非易失性存储器及其制造方法
公开(公告)号：US07700439B2
公开(公告)日：2010-04-20
申请号：US11376410
申请日：2006-03-15
申请人： Erwin J. Prinz , Ko-Min Chang , Robert F. Steimle
发明人： Erwin J. Prinz , Ko-Min Chang , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , B82Y10/00 , H01L21/28273 , H01L27/115
摘要： A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process with which to form silicided surfaces on both the select gate electrode and the control gate electrode.
摘要翻译：存储器件形成在半导体衬底上。选择栅电极和控制栅电极彼此相邻地形成。选择栅极电极或控制栅电极中的一个相对于另一个凹陷。该凹槽允许用于在选择栅极电极和控制栅极电极上形成硅化物表面的可制造工艺。

16. 发明授权

US07619275B2 Process for forming an electronic device including discontinuous storage elements 失效
标题翻译：用于形成包括不连续存储元件的电子设备的方法
公开(公告)号：US07619275B2
公开(公告)日：2009-11-17
申请号：US11188935
申请日：2005-07-25
申请人： Michael A. Sadd , Ko-Min Chang , Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
发明人： Michael A. Sadd , Ko-Min Chang , Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L21/7624 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336
摘要： A process for forming an electronic device can include forming a trench within a substrate, wherein the trench includes a wall and a bottom. The process can also include including forming a portion of discontinuous storage elements that lie within the trench, and forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
摘要翻译：用于形成电子器件的方法可以包括在衬底内形成沟槽，其中沟槽包括壁和底部。该方法还可以包括形成位于沟槽内的不连续存储元件的一部分，以及在形成不连续存储元件之后在沟槽内形成第一栅电极。至少一个不连续的存储元件位于第一栅电极的上表面和衬底的主表面之间的海拔处的沟槽的壁处。该工艺还可以包括形成覆盖在第一栅电极和衬底的主表面上的第二栅电极。

17. 发明申请

US20070018222A1 Electronic device including discontinuous storage elements 有权
标题翻译：电子设备包括不连续的存储元件
公开(公告)号：US20070018222A1
公开(公告)日：2007-01-25
申请号：US11188999
申请日：2005-07-25
申请人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
发明人： Michael Sadd , Ko-Min Chang , Gowrishankar Chindalore , Cheong Hong , Craig Swift
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译：电子设备可以包括位于沟槽内的不连续存储元件。在一个实施例中，电子设备可以包括具有包括壁和底部的沟槽的衬底。电子设备还可以包括位于沟槽内的不连续存储元件的一部分。电子器件还可以包括第一栅电极，其中至少一个不连续存储元件沿着沟槽的壁位于第一栅电极的上表面和衬底的主表面之间的高度处。电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。

18. 发明授权

US5706228A Method for operating a memory array 失效
标题翻译：操作存储器阵列的方法
公开(公告)号：US5706228A
公开(公告)日：1998-01-06
申请号：US603939
申请日：1996-02-20
申请人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
发明人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
IPC分类号： G11C16/04 , G11C16/10 , G11C11/40
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10
摘要： A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.
摘要翻译：具有选定的存储单元（10）和未选择的存储单元（30）的存储器阵列（25）被编程和读取。存储器阵列（25）中的每个存储单元包含隔离晶体管（22）和浮动栅极晶体管（23）。为了对所选择的存储单元（10）进行编程，将编程电压施加到控制栅极线（21），漏极线（14），隔离线（19）和源极线（12）。为了减小漏极干扰问题的影响，未选择的存储单元（30）的栅极端子（32）被保持在正电压。为了读取所选择的存储单元（10），读取电压被施加到未选择存储单元（30）的隔离栅极线（31），其确保未选择的存储单元（30）不导通或有助于漏电流和功耗在读操作期间。

19. 发明申请

US20140295639A1 FIELD FOCUSING FEATURES IN A RERAM CELL 有权
标题翻译： RERAM细胞中的场聚焦特征
公开(公告)号：US20140295639A1
公开(公告)日：2014-10-02
申请号：US14301900
申请日：2014-06-11
申请人： FENG ZHOU , Frank K. Baker, JR. , Ko-Min Chang , Cheong Min Hong
发明人： FENG ZHOU , Frank K. Baker, JR. , Ko-Min Chang , Cheong Min Hong
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/146 , H01L45/1675
摘要： A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.
摘要翻译：一种电阻随机存取存储器（ReRAM）单元，包括在第一导电电极上的第一导电电极和介电存储材料层。电介质存储材料层有利于在将细丝形成电压施加到电池时形成导电细丝。电池包括位于介电存储材料层上的第二导电电极和包括与电介质存储材料层接触并与第一导电电极或第二导电电极接触的多个纳米团簇的导电纳米团簇层（911,1211）。

20. 发明授权

US08779405B2 Field focusing features in a ReRAM cell 有权
标题翻译： ReRAM单元中的场聚焦功能
公开(公告)号：US08779405B2
公开(公告)日：2014-07-15
申请号：US13486690
申请日：2012-06-01
申请人： Feng Zhou , Frank K. Baker, Jr. , Ko-Min Chang , Cheong Min Hong
发明人： Feng Zhou , Frank K. Baker, Jr. , Ko-Min Chang , Cheong Min Hong
IPC分类号： H01L29/02
CPC分类号： H01L45/16 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/146 , H01L45/1675
摘要： A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.
摘要翻译：一种电阻随机存取存储器（ReRAM）单元，包括在第一导电电极上的第一导电电极和介电存储材料层。电介质存储材料层有利于在将细丝形成电压施加到电池时形成导电细丝。电池包括位于介电存储材料层上的第二导电电极和包括与电介质存储材料层接触并与第一导电电极或第二导电电极接触的多个纳米团簇的导电纳米团簇（911,1211）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式