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11. 发明申请

US20050221591A1 Method of forming high-quality relaxed SiGe alloy layers on bulk Si substrates 审中-公开
标题翻译：在大量Si衬底上形成高品质的松弛SiGe合金层的方法
公开(公告)号：US20050221591A1
公开(公告)日：2005-10-06
申请号：US10818572
申请日：2004-04-06
申请人： Stephen Bedell , Huajie Chen , Joel de Souza , Keith Fogel , Devendra Sadana , Ghavam Shahidi
发明人： Stephen Bedell , Huajie Chen , Joel de Souza , Keith Fogel , Devendra Sadana , Ghavam Shahidi
IPC分类号： C30B1/00 , H01L21/20 , H01L21/3063 , H01L21/36 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/3063 , H01L21/02381 , H01L21/0245 , H01L21/02513 , H01L21/02532 , H01L21/02658
摘要： A method of forming a high-quality relaxed SiGe alloy layer on a bulk Si-containing substrate is provided. The method of the present invention includes growing a strained SiGe alloy layer on a Si-containing substrate that has a porous Si-containing layer at or near the surface of the Si-containing substrate. The porous layer is formed by an electrolytic anodization process. The pores create free volume below the strained SiGe layer which can serve to accommodate strain relaxation during SiGe deposition or a subsequent heating step. The subsequent heating step is optional and is performed to further increase the relaxation of the SiGe alloy layer. The buried porous structure allows for a unique relaxation mechanism compared to prior art methods.
摘要翻译：提供了在体积含Si衬底上形成高品质的弛豫SiGe合金层的方法。本发明的方法包括在含Si衬底上生长应变SiGe合金层，该Si基合金层在含Si衬底的表面处或附近具有多孔含Si层。多孔层通过电解阳极氧化处理形成。孔隙在应变SiGe层之下产生自由体积，其可用于在SiGe沉积或随后的加热步骤期间适应应变松弛。随后的加热步骤是可选的并且进行以进一步增加SiGe合金层的松弛。与现有技术方法相比，埋入的多孔结构允许独特的松弛机制。

12. 发明申请

US20060244068A1 Field effect transistor with mixed-crystal-orientation channel and source/drain regions 有权
标题翻译：具有混晶取向沟道和源极/漏极区的场效应晶体管
公开(公告)号：US20060244068A1
公开(公告)日：2006-11-02
申请号：US11116053
申请日：2005-04-27
申请人： Joel Desouza , Devendra Sadana , Katherine Saenger , Chun-yung Sung , Min Yang , Haizhou Yin
发明人： Joel Desouza , Devendra Sadana , Katherine Saenger , Chun-yung Sung , Min Yang , Haizhou Yin
IPC分类号： H01L27/12
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/7624 , H01L21/823807 , H01L21/8258 , H01L27/0605 , H01L27/0922 , H01L27/1203 , H01L29/045 , H01L29/66636 , H01L29/7833
摘要： Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.
摘要翻译：混合定向衬底允许制造互补金属氧化物半导体（CMOS）电路，其中n型场效应晶体管（nFET）以优选的电子迁移率的半导体取向设置，并且p型场效应晶体管（pFET）以半导体方向设置，其对于空穴迁移率是最佳的。本发明公开了完全形成在最佳半导体取向中的FET的性能优点可以通过仅需要将器件的沟道设置在具有最佳取向的半导体中来实现。描述了各种新的FET结构，其特征在于，至少部分FET通道的FET的源极和/或漏极的至少一部分具有不同的取向。可以并入其中可并入这些新的FET的混合基板及其制造方法。

13. 发明申请

US20080206965A1 STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY 审中-公开
标题翻译：通过从Si（1-x-y）GexCy合金中制备碳制成的应变硅
公开(公告)号：US20080206965A1
公开(公告)日：2008-08-28
申请号：US11679308
申请日：2007-02-27
申请人： Oleg Gluschenkov , Yaocheng Liu , Alexander Reznicek , Devendra Sadana
发明人： Oleg Gluschenkov , Yaocheng Liu , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L21/20
CPC分类号： H01L29/4983 , H01L21/02529 , H01L21/02532 , H01L21/02667 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Disclosed herein is a method of preparing strained silicon comprising annealing a carbon-doped silicon-germanium (SiGe:C) alloy containing region disposed adjacent to a silicon region, wherein the lattice constant of the SiGe:C alloy after annealing is greater than that of the SiGe:C alloy prior to annealing. The method can be used to prepare articles including metal oxide semiconductor field effect transistor (MOSFET) devices.
摘要翻译：本发明公开了一种制备应变硅的方法，包括退火邻近硅区的碳掺杂硅 - 锗（SiGe：C）合金含有区域，其中退火后SiGe：C合金的晶格常数大于退火之前的SiGe：C合金。该方法可用于制备包括金属氧化物半导体场效应晶体管（MOSFET）器件的制品。

14. 发明申请

US20080050887A1 METHOD FOR FABRICATING SiGe-ON-INSULATOR (SGOI) AND Ge-ON-INSULATOR (GOI) SUBSTRATES 有权
标题翻译：用于制造SiGe-ON绝缘体（SGOI）和Ge-ON-Insulator（GOI）衬底的方法
公开(公告)号：US20080050887A1
公开(公告)日：2008-02-28
申请号：US11924207
申请日：2007-10-25
申请人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

15. 发明申请

US20060275961A1 Strained silicon CMOS on hybrid crystal orientations 有权
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US20060275961A1
公开(公告)日：2006-12-07
申请号：US11492271
申请日：2006-07-25
申请人： Kevin Chan , Meikei Ieong , Alexander Reznicek , Devendra Sadana , Leathen Shi , Min Yang
发明人： Kevin Chan , Meikei Ieong , Alexander Reznicek , Devendra Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/84
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

16. 发明申请

US20050093100A1 Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates 有权
标题翻译：用于制造绝缘体上硅（SGOI）和绝缘体上（GeI）绝缘体（GOI）基板的方法
公开(公告)号：US20050093100A1
公开(公告)日：2005-05-05
申请号：US10700085
申请日：2003-11-03
申请人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/762 , H01L27/12 , H01L27/144 , H01L31/0232 , H01L31/028 , H01L31/0352 , H01L31/105 , H01L31/18 , H01L31/117
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

17. 发明申请

US20100006985A1 FORMATION OF SOI BY OXIDATION OF SILICON WITH ENGINEERED POROSITY GRADIENT 失效
标题翻译：通过氧化硅与工程化孔隙度梯度形成SOI
公开(公告)号：US20100006985A1
公开(公告)日：2010-01-14
申请号：US12170459
申请日：2008-07-10
申请人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
发明人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L21/76245
摘要： A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer.
摘要翻译：提供了一种制造绝缘体上硅衬底的方法。这种方法可以包括将高p型掺杂的含硅层外延生长到衬底的下面的半导体区域的主表面上。随后，可以在p型高掺杂外延层的主表面上外延生长非高度p型掺杂的含硅层，以覆盖高度p型掺杂的外延层。上覆非高p型掺杂外延层可以具有基本上低于高p型掺杂外延层的掺杂剂浓度的掺杂剂浓度。然后可以通过氧化由非高p型掺杂的外延层覆盖的高p型掺杂外延层的至少一部分来选择性地处理衬底以形成掩埋氧化物层，将覆盖的单晶半导体层从底层半导体区域。可以在非高p型掺杂外延层同时退火的同时执行这种处理。

18. 发明申请

US20070235759A1 CMOS process with Si gates for nFETs and SiGe gates for pFETs 审中-公开
标题翻译：用于nFET的Si栅极的CMOS工艺和用于pFET的SiGe栅极
公开(公告)号：US20070235759A1
公开(公告)日：2007-10-11
申请号：US11401672
申请日：2006-04-11
申请人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
发明人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
IPC分类号： H01L31/00
CPC分类号： H01L21/2807 , H01L21/823842
摘要： An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.
摘要翻译：提供了用于在同一半导体衬底上为pFET器件提供nFET器件的Si栅极和SiGe栅极的集成方案。该集成方案包括首先提供材料堆叠，其从底部到顶部包括在半导体衬底的表面上的栅极电介质，Si膜和硬掩模，其包括至少一个nFET器件区域和至少一个pFET器件区域。接下来，将硬掩模从至少一个pFET器件区域中的材料堆叠中选择性地去除，从而暴露Si膜。暴露的Si膜然后被转换成SiGe膜，此后在至少一个nFET器件区域中形成至少一个nFET器件，并且在至少一个pFET器件区域中形成至少一个pFET器件。根据本发明，至少一个nFET器件包括Si栅极，并且至少一个pFET包括SiGe栅极。

19. 发明授权

US07772096B2 Formation of SOI by oxidation of silicon with engineered porosity gradient 失效
标题翻译：通过工程化孔隙度梯度的硅氧化形成SOI
公开(公告)号：US07772096B2
公开(公告)日：2010-08-10
申请号：US12170459
申请日：2008-07-10
申请人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
发明人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/76245
摘要： A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer.
摘要翻译：提供了一种制造绝缘体上硅衬底的方法。这种方法可以包括将高p型掺杂的含硅层外延生长到衬底的下面的半导体区域的主表面上。随后，可以在p型高掺杂外延层的主表面上外延生长非高度p型掺杂的含硅层，以覆盖高度p型掺杂的外延层。上覆非高p型掺杂外延层可以具有基本上低于高p型掺杂外延层的掺杂剂浓度的掺杂剂浓度。然后可以通过氧化由非高p型掺杂的外延层覆盖的高p型掺杂外延层的至少一部分来选择性地处理衬底以形成掩埋氧化物层，将覆盖的单晶半导体层从底层半导体区域。可以在非高p型掺杂外延层同时退火的同时执行这种处理。

20. 发明申请

US20070238276A1 Control of poly-Si depletion in CMOS via gas phase doping 失效
标题翻译：通过气相掺杂控制CMOS中的多晶硅耗尽
公开(公告)号：US20070238276A1
公开(公告)日：2007-10-11
申请号：US11402177
申请日：2006-04-11
申请人： Yaocheng Liu , Alexander Reznicek , Devendra Sadana
发明人： Yaocheng Liu , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L21/4763
CPC分类号： H01L21/823842 , H01L21/28035 , H01L21/32155 , H01L29/4916
摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.
摘要翻译：提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。本发明还提供了使用本文所述的气相掺杂技术制造的包括例如nFET和/或pFET的CMOS结构。

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