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11. 发明授权

US06221562B1 Resist image reversal by means of spun-on-glass 失效
标题翻译：通过旋转玻璃抵抗图像反转
公开(公告)号：US06221562B1
公开(公告)日：2001-04-24
申请号：US09192137
申请日：1998-11-13
申请人： Diane C. Boyd , Toshiharu Furukawa , Steven J. Holmes , William H. Ma , Paul A. Rabidoux , David V. Horak
发明人： Diane C. Boyd , Toshiharu Furukawa , Steven J. Holmes , William H. Ma , Paul A. Rabidoux , David V. Horak
IPC分类号： G03F700
CPC分类号： H01L21/0337 , G03F7/40 , H01L21/0274 , H01L21/32139
摘要： An image reversal method of turning hybrid photoresist spaces into resist lines for sub-feature size applications. The sub-feature size space width of the high resolution hybrid photoresist is largely independent of the lithographic process and mask reticles. These sub-feature size spaces formed by the hybrid resist are then turned into sub-feature size lines using Spin-On-Glass, SOG. The SOG is first coated over the entire patterned hybrid resist to fill in the hybrid spaces and cover the photoresist. SOG is then recessed back to expose the photoresist layer. The exposed photoresist is then removed. The sub-feature size lines are then left behind as a mask to pattern the same onto the underlying films on the substrate.
摘要翻译：将混合光致抗蚀剂空间转换成用于子特征尺寸应用的抗蚀剂线的图像反转方法。高分辨率混合光致抗蚀剂的子特征尺寸空间宽度在很大程度上独立于光刻工艺和掩模掩模版。然后，使用旋转玻璃，SOG将由混合抗蚀剂形成的这些子特征尺寸空间变成子特征尺寸线。 SOG首先涂覆在整个图案化的混合抗蚀剂上以填充混合空间并覆盖光致抗蚀剂。然后将SOG凹进来露出光致抗蚀剂层。然后除去曝光的光致抗蚀剂。然后将子特征尺寸线作为掩模留下以将其图案化到衬底上的下面的膜上。

12. 发明授权

US6143635A Field effect transistors with improved implants and method for making such transistors 失效
标题翻译：具有改进的植入物的场效应晶体管和制造这种晶体管的方法
公开(公告)号：US6143635A
公开(公告)日：2000-11-07
申请号：US374519
申请日：1999-08-16
申请人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Yuan Taur , William C. Wille
发明人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Yuan Taur , William C. Wille
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66583 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L29/66537
摘要： Metal oxide semiconductor field effect transistor (MOSFET) including a drain region and a source region adjacent to a channel region. A gate oxide is situated on the channel region and a gate conductor with vertical side walls is placed on the gate oxide. The MOSFET further includes a threshold adjust implant region and/or punch through implant region being aligned with respect to the gate conductor and limited to an area underneath the gate conductor. Such a MOSFET can be made using the following method: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack having the lateral size and shape of a gate hole to be formed; defining the gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; implanting threshold adjust dopants and/or punch through dopants through the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering portions of the semiconductor structure surrounding the gate hole; and removing at least part of the dielectric stack.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）包括漏极区域和与沟道区域相邻的源极区域。栅极氧化物位于沟道区域上，并且具有垂直侧壁的栅极导体被放置在栅极氧化物上。 MOSFET还包括阈值调整注入区域和/或冲孔穿入注入区域，其相对于栅极导体对齐并且限制在栅极导体下方的区域。这样的MOSFET可以使用以下方法制造：在半导体结构上形成介电堆叠; 在所述电介质堆叠上限定具有要形成的栅极孔的横向尺寸和形状的蚀刻窗口; 通过使用反应离子蚀刻（RIE）工艺将蚀刻窗口转移到电介质堆叠中来限定电介质叠层中的栅极孔; 植入阈值调节掺杂剂和/或穿过掺杂剂通过栅极孔; 沉积栅极导体，使其填充栅极孔; 去除覆盖围绕门孔的半导体结构的部分的栅极导体; 以及去除所述电介质叠层的至少一部分。

13. 发明授权

US6040214A Method for making field effect transistors having sub-lithographic gates with vertical side walls 失效
标题翻译：用于制造具有垂直侧壁的子光刻栅的场效应晶体管的方法
公开(公告)号：US6040214A
公开(公告)日：2000-03-21
申请号：US26261
申请日：1998-02-19
申请人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Yuan Taur , William C. Wille
发明人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Yuan Taur , William C. Wille
IPC分类号： H01L21/033 , H01L21/28 , H01L21/336 , H01L21/762 , H01L29/423 , H01L21/8242 , H01L21/20
CPC分类号： H01L29/66583 , H01L21/0337 , H01L21/0338 , H01L21/28123 , H01L21/76224 , H01L29/42372
摘要： A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.
摘要翻译：一种形成场效应晶体管（FET）的方法，特别是金属氧化物场效应晶体管（MOSFET），包括以下步骤：在半导体结构上形成电介质叠层; 在电介质堆叠上限定蚀刻窗口; 通过使用反应离子蚀刻（RIE）工艺将蚀刻窗口转移到电介质堆叠中来在电介质叠层中限定栅极孔; 沉积侧壁层; 从介质堆叠和门孔的水平表面去除侧壁层，使得保留侧壁间隔物，这减小了闸门孔的横向尺寸; 沉积栅极导体，使其填充栅极孔; 去除覆盖围绕栅极孔的半导体结构的部分的栅极导体; 去除所述电介质叠层的至少一部分; 并移除侧壁间隔物。

14. 发明授权

US07655557B2 CMOS silicide metal gate integration 失效
标题翻译： CMOS硅化物金属栅极集成
公开(公告)号：US07655557B2
公开(公告)日：2010-02-02
申请号：US12145113
申请日：2008-06-24
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

15. 发明申请

US20080251813A1 HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS 审中-公开
标题翻译： HETERO-INTEGRATED应变硅n-和p- MOSFET
公开(公告)号：US20080251813A1
公开(公告)日：2008-10-16
申请号：US12140612
申请日：2008-06-17
申请人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
发明人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
IPC分类号： H01L29/778
CPC分类号： H01L21/26506 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/26513 , H01L21/823807 , H01L29/1054 , H01L29/7842 , Y10S438/938
摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.
摘要翻译：本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。然后在含有受损区域的含Si衬底上形成应变SiGe合金。然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

16. 发明授权

US06982196B2 Oxidation method for altering a film structure and CMOS transistor structure formed therewith 失效
标题翻译：用于改变由其形成的膜结构和CMOS晶体管结构的氧化方法
公开(公告)号：US06982196B2
公开(公告)日：2006-01-03
申请号：US10605889
申请日：2003-11-04
申请人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
发明人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译：提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率另一个是NFET和PFET。

17. 发明授权

US06841831B2 Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process 有权
标题翻译：使用凹陷通道镶嵌栅极工艺，具有低源极和漏极电阻以及最小重叠电容的全耗尽SOI MOSFET
公开(公告)号：US06841831B2
公开(公告)日：2005-01-11
申请号：US10461821
申请日：2003-06-13
申请人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
发明人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
IPC分类号： H01L21/336 , H01L29/786 , H01L29/76
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78612
摘要： A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 μm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.
摘要翻译：提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。子0.05通道长度全耗尽的SOI MOSFET器件包括SOI结构，其至少包含具有第一厚度的沟道区和邻接其中存在第二厚度的源极/漏极区的SOI层，其中第二厚度为大于第一厚度，并且源/漏区具有存在于其上的自对准硅化物层。栅极区也存在于SOI层的顶部。

18. 发明授权

US06835633B2 SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer 失效
标题翻译：具有30-100埃埋层氧化物（BOX）的SOI晶片通过使用30-100薄氧化物作为结合层的晶片接合而产生
公开(公告)号：US06835633B2
公开(公告)日：2004-12-28
申请号：US10202329
申请日：2002-07-24
申请人： Diane C. Boyd , Hussein I. Hanafi , Erin C. Jones , Dominic J. Schepis , Leathen Shi
发明人： Diane C. Boyd , Hussein I. Hanafi , Erin C. Jones , Dominic J. Schepis , Leathen Shi
IPC分类号： H01L2176
CPC分类号： H01L21/76251 , H01L21/76243
摘要： A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.
摘要翻译：提供一种制造具有栅极质量薄的掩埋氧化物区域的SOI晶片的方法。通过在SOI衬底的含Si层的表面上形成基本上均匀的热氧化物来制造晶片，该衬底包括位于含Si层和含Si衬底层之间的掩埋氧化物区域。接下来，使用清洁方法在热氧化物上形成亲水性表面。提供具有亲水表面的载体晶片并且将其定位在基板附近，使得亲水表面彼此相邻。然后使用室温粘合将载体晶片粘合到基底上。进行退火工序，然后选择性地除去绝缘体上硅衬底的含硅衬底和掩埋氧化物区域以暴露含Si层。

19. 发明授权

US08669145B2 Method and structure for strained FinFET devices 有权
标题翻译：应变FinFET器件的方法和结构
公开(公告)号：US08669145B2
公开(公告)日：2014-03-11
申请号：US10710272
申请日：2004-06-30
申请人： Bruce B. Doris , Diane C. Boyd , Huilong Zhu
发明人： Bruce B. Doris , Diane C. Boyd , Huilong Zhu
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/41733 , H01L29/458 , H01L29/66795 , H01L29/7842
摘要： A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.
摘要翻译：形成电子器件的方法（和结构）包括在器件内形成至少一个局部应力源区域。

20. 发明授权

US07741166B2 Oxidation method for altering a film structure 失效
标题翻译：用于改变膜结构的氧化方法
公开(公告)号：US07741166B2
公开(公告)日：2010-06-22
申请号：US11318818
申请日：2005-12-27
申请人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
发明人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A method is provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A method is further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译：提供了一种方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。还提供了一种方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率另一个是NFET和PFET。

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