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1. 发明授权

US06982196B2 Oxidation method for altering a film structure and CMOS transistor structure formed therewith 失效
标题翻译：用于改变由其形成的膜结构和CMOS晶体管结构的氧化方法
公开(公告)号：US06982196B2
公开(公告)日：2006-01-03
申请号：US10605889
申请日：2003-11-04
申请人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
发明人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译：提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率另一个是NFET和PFET。

2. 发明授权

US07741166B2 Oxidation method for altering a film structure 失效
标题翻译：用于改变膜结构的氧化方法
公开(公告)号：US07741166B2
公开(公告)日：2010-06-22
申请号：US11318818
申请日：2005-12-27
申请人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
发明人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A method is provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A method is further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译：提供了一种方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。还提供了一种方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率另一个是NFET和PFET。

3. 发明授权

US07488658B2 Stressed semiconductor device structures having granular semiconductor material 有权
标题翻译：具有粒状半导体材料的强调半导体器件结构
公开(公告)号：US07488658B2
公开(公告)日：2009-02-10
申请号：US11531372
申请日：2006-09-13
申请人： Bruce B. Doris , Michael P. Belyansky , Diane C. Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
发明人： Bruce B. Doris , Michael P. Belyansky , Diane C. Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/7845 , H01L21/26513 , H01L21/2658 , H01L21/28035 , H01L21/28167 , H01L21/28247 , H01L21/324 , H01L21/823807 , H01L21/823842 , H01L29/1083 , H01L29/4925 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.
摘要翻译：一种半导体器件结构的制造方法，包括：提供基板，在所述基板上设置电极，在所述电极中形成凹部，所述凹部具有开口，在所述凹部内设置小晶粒半导体材料，覆盖所述开口以容纳小晶粒半导体材料，在凹陷内，然后退火所得结构。

4. 发明申请

US20080064172A1 STRESSED SEMICONDUCTOR DEVICE STRUCTURES HAVING GRANULAR SEMICONDUCTOR MATERIAL 有权
标题翻译：具有颗粒半导体材料的应力半导体器件结构
公开(公告)号：US20080064172A1
公开(公告)日：2008-03-13
申请号：US11531372
申请日：2006-09-13
申请人： Bruce B. Doris , Michael P. Belyansky , Diane C. Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
发明人： Bruce B. Doris , Michael P. Belyansky , Diane C. Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/7845 , H01L21/26513 , H01L21/2658 , H01L21/28035 , H01L21/28167 , H01L21/28247 , H01L21/324 , H01L21/823807 , H01L21/823842 , H01L29/1083 , H01L29/4925 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.
摘要翻译：一种半导体器件结构的制造方法，包括：提供基板，在所述基板上设置电极，在所述电极中形成凹部，所述凹部具有开口，在所述凹部内设置小晶粒半导体材料，覆盖所述开口以容纳小晶粒半导体材料，在凹陷内，然后退火所得结构。

5. 发明授权

US07202516B2 CMOS transistor structure including film having reduced stress by exposure to atomic oxygen 失效
标题翻译： CMOS晶体管结构包括通过暴露于原子氧而具有减小的应力的膜
公开(公告)号：US07202516B2
公开(公告)日：2007-04-10
申请号：US11318844
申请日：2005-12-27
申请人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
发明人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L29/80
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译：提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率另一个是NFET和PFET。

6. 发明授权

US07247569B2 Ultra-thin Si MOSFET device structure and method of manufacture 失效
标题翻译：超薄Si MOSFET器件结构及制造方法
公开(公告)号：US07247569B2
公开(公告)日：2007-07-24
申请号：US10725848
申请日：2003-12-02
申请人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
发明人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
IPC分类号： H01L21/302
CPC分类号： H01L21/28194 , H01L21/26533 , H01L21/28202 , H01L29/1083 , H01L29/49 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/78
摘要： The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.
摘要翻译：本发明包括用于形成超薄沟道MOSFET的方法和由其制造的超薄沟道MOSFET。具体地说，该方法包括：在SOI层的下方提供具有掩埋绝缘层的SOI衬底; 在SOI层顶上形成焊盘堆叠; 通过所述垫堆叠的顶部形成具有通道的块掩模; 在所述掩埋绝缘层的顶部上的所述SOI层中提供局部氧化物区域，从而使所述SOI层的一部分变薄，所述局部氧化物区域与所述沟道通孔自对准; 在通道通道中形成一个门; 至少去除阻挡掩模; 以及在与SOI层的薄化部分邻接的SOI层中形成源极/漏极延伸部。提供局部氧化物区域还包括通过沟道通孔将氧掺杂剂注入到SOI层的一部分中; 并退火掺杂剂以产生局部氧化物区域。

7. 发明授权

US06911383B2 Hybrid planar and finFET CMOS devices 失效
标题翻译：混合平面和finFET CMOS器件
公开(公告)号：US06911383B2
公开(公告)日：2005-06-28
申请号：US10604097
申请日：2003-06-26
申请人： Bruce B. Doris , Diane C. Boyd , Meikei Ieong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
发明人： Bruce B. Doris , Diane C. Boyd , Meikei Ieong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/49 , H01L29/786 , H01L21/3205
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.
摘要翻译：本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上，绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。还提供了一种形成集成电路的方法。在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

8. 发明授权

US08669145B2 Method and structure for strained FinFET devices 有权
标题翻译：应变FinFET器件的方法和结构
公开(公告)号：US08669145B2
公开(公告)日：2014-03-11
申请号：US10710272
申请日：2004-06-30
申请人： Bruce B. Doris , Diane C. Boyd , Huilong Zhu
发明人： Bruce B. Doris , Diane C. Boyd , Huilong Zhu
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/41733 , H01L29/458 , H01L29/66795 , H01L29/7842
摘要： A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.
摘要翻译：形成电子器件的方法（和结构）包括在器件内形成至少一个局部应力源区域。

9. 发明授权

US07482243B2 Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique 失效
标题翻译：超薄Si沟道MOSFET采用自对准氧注入和镶嵌技术
公开(公告)号：US07482243B2
公开(公告)日：2009-01-27
申请号：US11436756
申请日：2006-05-18
申请人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
发明人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
IPC分类号： H01L21/76 , H01L21/338 , H01L21/84 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78609 , H01L29/78684
摘要： The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.
摘要翻译：本发明提供一种形成具有低外部电阻的薄沟道MOSFET的方法。该方法包括在基板的顶部形成伪栅极区域; 通过所述伪栅极注入形成氧化物的掺杂剂，以在与沟道区域的伪栅极区对准的衬底的一部分中产生局部氧化物区域; 形成邻接所述沟道区的源/漏扩展区; 并用栅极导体代替虚拟栅极。

10. 发明授权

US07250658B2 Hybrid planar and FinFET CMOS devices 有权
标题翻译：混合平面和FinFET CMOS器件
公开(公告)号：US07250658B2
公开(公告)日：2007-07-31
申请号：US11122193
申请日：2005-05-04
申请人： Bruce B. Doris , Diane C. Boyd , Meikei Leong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
发明人： Bruce B. Doris , Diane C. Boyd , Meikei Leong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
IPC分类号： H01L29/772
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.
摘要翻译：本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上，绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。还提供了一种形成集成电路的方法。在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

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