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11. 发明授权

US08250308B2 Cache coherency protocol with built in avoidance for conflicting responses 失效
标题翻译：缓存一致性协议内置避免冲突的响应
公开(公告)号：US08250308B2
公开(公告)日：2012-08-21
申请号：US12031977
申请日：2008-02-15
申请人： Vesselina K. Papazova , Ekaterina M. Ambroladze , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
发明人： Vesselina K. Papazova , Ekaterina M. Ambroladze , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership state of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.
摘要翻译：该方法包括：当处理器请求遇到本地高速缓存未命中时，向请求节点中的高速缓存发起处理器请求并将处理器请求广播到远程节点，执行每个远程高速缓存的目录搜索以确定目标行的地址的状态，以及指定地址的所有权状态，将目标行的状态返回到请求节点并形成组合响应，并将组合的响应广播到每个远程节点。在获取操作期间，当目录搜索指示远程节点上的IM或目标存储器节点时，数据来自相应的远程高速缓存并且在保护数据的同时被转发到请求节点，并且在存储操作期间，数据是源自请求节点，并且在一致性被建立之后被转发到IM或目标存储器节点时被保护。

12. 发明授权

US07934059B2 Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetching 有权
标题翻译：方法，系统和计算机程序产品，用于防止具有推测性内存提取的多节点系统中的锁定和停顿条件
公开(公告)号：US07934059B2
公开(公告)日：2011-04-26
申请号：US12021781
申请日：2008-01-29
申请人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
发明人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.
摘要翻译：一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到解决冲突的点，而不发出另一个推测性的内存提取请求。随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

13. 发明申请

US20090193198A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PREVENTING LOCKOUT AND STALLING CONDITIONS IN A MULTI-NODE SYSTEM WITH SPECULATIVE MEMORY FETCHING 有权
标题翻译：方法，系统和计算机程序产品，用于在具有分析存储器故障的多节点系统中防止闭锁和停放条件
公开(公告)号：US20090193198A1
公开(公告)日：2009-07-30
申请号：US12021781
申请日：2008-01-29
申请人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
发明人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.
摘要翻译：一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到解决冲突的点，而不发出另一个推测性的内存提取请求。随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

14. 发明授权

US06738872B2 Clustered computer system with deadlock avoidance 有权
标题翻译：具有死锁避免的集群计算机系统
公开(公告)号：US06738872B2
公开(公告)日：2004-05-18
申请号：US09746686
申请日：2000-12-22
申请人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak , Adrian Eric Seigler
发明人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak , Adrian Eric Seigler
IPC分类号： G06F1200
CPC分类号： G06F9/524
摘要： A remote resource management system for managing resources in a symmetrical multiprocessing environment having a plurality of clusters of symmetric multiprocessors each of which provides interfaces between cluster nodes of the symmetric multiprocessor system with a local interface and an interface controller. One or more remote storage controllers each has a local interface controller and a local-to-remote data bus. A remote fetch controller is responsible for processing data accesses across the clusters and a remote store controller is responsible for processing data accesses across the clusters. These controllers work in conjunction to provide a deadlock avoidance system for preventing hangs.
摘要翻译：一种用于在具有多个对称多处理器群集的对称多处理环境中管理资源的远程资源管理系统，每个处理器集群在对称多处理器系统的群集节点与本地接口和接口控制器之间提供接口。一个或多个远程存储控制器各自具有本地接口控制器和本地到远程的数据总线。远程提取控制器负责处理跨集群的数据访问，远程存储控制器负责处理跨集群的数据访问。这些控制器协同工作，提供一个防止挂起的死锁避免系统。

15. 发明授权

US06738870B2 High speed remote storage controller 失效
标题翻译：高速远程存储控制器
公开(公告)号：US06738870B2
公开(公告)日：2004-05-18
申请号：US09745593
申请日：2000-12-22
申请人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak
发明人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak
IPC分类号： G06F1200
CPC分类号： G06F15/17381
摘要： A high speed remote storage controller system for a computer system has cluster nodes of symmetric multiprocessors. A plurality of clusters of symmetric multiprocessors each of has a plurality of processors, a shared cache memory, a plurality of I/O adapters and a main memory accessible from the cluster. Each cluster has an interface for passing data between cluster nodes of the symmetric multiprocessor system. Each cluster has a local interface and interface controller. The system provides one or more remote storage controllers each having a local interface controller and a local-to-remote data bus. A remote resource manager manages the interface between clusters of symmetric multiprocessors. The remote store controller is responsible for processing data accesses across a plurality of clusters and processes data storage operations involving shared memory. A macro is provided for processing a plurality of simultaneous data storage operations either synchronously through interaction with a sequential multistage centralized pipeline to serialize requests and provide address interlocking services or asynchronously whereby main memory accesses bypass a centralized system pipeline. These accesses can occur in parallel with other remote storage operations.
摘要翻译：用于计算机系统的高速远程存储控制器系统具有对称多处理器的集群节点。多个对称多处理器群集具有多个处理器，共享高速缓存存储器，多个I / O适配器和可从群集访问的主存储器。每个集群都有一个用于在对称多处理器系统的集群节点之间传递数据的接口。每个集群都有一个本地接口和接口控制器。该系统提供一个或多个远程存储控制器，每个具有本地接口控制器和本地到远程的数据总线。远程资源管理器管理对称多处理器群集之间的接口。远程存储控制器负责处理跨多个集群的数据访问，并处理涉及共享存储器的数据存储操作。提供宏，用于通过与顺序多级集中式流水线的交互同步地处理多个同时的数据存储操作，以串行化请求并提供地址互锁服务或异步地使主存储器访问绕过集中式系统流水线。这些访问可能与其他远程存储操作并行发生。

16. 发明授权

US06988173B2 Bus protocol for a switchless distributed shared memory computer system 失效
标题翻译：总线协议用于无交换分布式共享内存计算机系统
公开(公告)号：US06988173B2
公开(公告)日：2006-01-17
申请号：US10435878
申请日：2003-05-12
申请人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
发明人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system. The bus protocol also allows data to be returned on one of the two rings, with the ring selection determined by the relative placement of the source and destination nodes on each ring, in order to control latency and data bus utilization.
摘要翻译：公开了一种用于由多个节点组成的对称多处理计算机系统的总线协议，每个节点包含多个处理器，I / O设备，主存储器和包括具有顶级高速缓存的集成交换机的系统控制器。节点通过双同心环拓扑互连。总线协议用于以一种允许部分一致性结果与窥探请求和地址并行传送的方式来交换窥探请求和地址，数据，相关性信息和节点之间的操作状态，因为操作沿着每个环转发。每个节点将其自身的一致性结果与在将窥探请求转发之前接收的部分一致性结果相结合，将地址和更新的部分一致性结果合并到环上的下一个节点。该协议允许系统中的每个节点查看最终的一致性结果，而不需要请求节点将这些结果广播到系统中的所有其他节点。总线协议还允许在两个振铃中的一个上返回数据，其中环选择由每个振铃上的源节点和目的节点的相对位置确定，以便控制等待时间和数据总线的利用。

17. 发明授权

US6151655A Computer system deadlock request resolution using timed pulses 失效
标题翻译：使用定时脉冲的计算机系统死锁请求分辨率
公开(公告)号：US6151655A
公开(公告)日：2000-11-21
申请号：US70432
申请日：1998-04-30
申请人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
发明人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
IPC分类号： G06F15/177 , G06F9/46 , G06F9/52 , G06F12/00
CPC分类号： G06F9/524
摘要： Disclosed is a hardware mechanism for detecting and avoiding potential deadlocks among requestors in a multiprocessor system, consisting of a plurality of CP's and I/O adapters connected to one or more shared storage controllers (SC's). Requests to each storage controller originate from external sources such as the CP's, the I/O adapters, and the other SC, as well as from internal sources, such as the hardware facilities used to process fetches and stores between the SC and main memory. All requests must be granted priority before beginning to execute, using a ranked priority order scheme. Specific sequences of requests may cause deadlocks, either due to high-priority requests using priority cycles and locking out low-priority requests, or as a result of requests of any priority level busying resources needed for the completion of other requests. The deadlock resolution mechanism described here monitors the length of time a request has been valid in the storage controller without completing, by checking the request register valid bits and utilizing a timed pulse, which is a subset of the pulse used to detect hangs within the SC. If the valid bit for a request register is on, and two timed pulses are received, an internal hang detect latch is set. If the valid bit is reset at any time, the detection logic and the internal hang detect latch are reset. When the internal hang detect latch is set, requests in progress are allowed to complete, and new requests are held in an inactive state, until the request which detected the internal hang is able to complete.
摘要翻译：公开了一种用于检测和避免多处理器系统中的请求者之间潜在的死锁的硬件机制，其由连接到一个或多个共享存储控制器（SC）的多个CP和I / O适配器组成。对每个存储控制器的请求源自诸如CP，I / O适配器和其他SC的外部源，以及来自内部源（例如用于处理SC和主存储器之间的获取和存储的硬件设施）。所有请求必须在开始执行之前被赋予优先级，使用排名优先顺序方案。特定的请求序列可能会由于高优先权请求使用优先级周期和锁定低优先级请求而导致死锁，或者由于完成其他请求所需的任何优先级级别的资源请求而产生死锁。这里描述的死锁解析机制通过检查请求寄存器有效位并利用定时脉冲来监视存储控制器中的请求已经有效的时间长度，并且使用定时脉冲，定时脉冲是用于检测SC内的挂起的脉冲的子集。如果请求寄存器的有效位为开，并且接收到两个定时脉冲，则设置内部挂起检测锁存器。如果有效位在任何时候被复位，则检测逻辑和内部挂起检测锁存器被复位。当设置内部挂起检测锁存器时，允许正在进行的请求完成，并且新的请求保持在非活动状态，直到检测到内部挂起的请求能够完成为止。

18. 发明授权

US6073182A Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic 失效
标题翻译：使用全局挂起脉冲逻辑解决多处理器中竞争请求之间的死锁的方法
公开(公告)号：US6073182A
公开(公告)日：2000-06-06
申请号：US70664
申请日：1998-04-30
申请人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
发明人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
IPC分类号： G06F13/16 , G06F15/16 , G06F15/173
CPC分类号： G06F13/1663
摘要： A method using a global hang pulse logic mechanism detects and resolves deadlocks among requesters to the storage controller of a symmetric multiprocessor system in which multiple central processors and I/O adapters are connected to one or more shared storage controllers. Deadlocks may occur in such a system due to specific sequences of requests, either because high priority requests use priority cycles and lock out low priority requests, or because requests of any priority level make resources needed for the completion of other requests too busy. The mechanism logic monitors the length of time a request has been valid in the storage controller without completing, by checking the request register valid bits, and by utilizing a timed pulse which is a subset of the pulse used to detect hangs within the storage controller. If the valid bit is reset at any time detection logic and an internal hang detect latch is set, Logic which allows requests in progress to complete, and holds new requests in an inactive state is activated when the internal hang latch is set and remains active until the request which detected the internal hang is able to complete, thus resetting the internal hang detect latch.
摘要翻译：使用全局挂起脉冲逻辑机制的方法检测并解决请求者之间的死锁到其中多个中央处理器和I / O适配器连接到一个或多个共享存储控制器的对称多处理器系统的存储控制器。由于高优先级请求使用优先级周期并锁定低优先级请求，或者由于任何优先级的请求使得完成其他请求太繁忙所需的资源，因此在这种系统中可能会由于特定的请求序列而在这样的系统中发生死锁。机制逻辑监视存储控制器中的请求已经有效的时间长度，而不需要通过检查请求寄存器有效位以及利用作为用于检测存储控制器内的挂起的脉冲的子集的定时脉冲来完成。如果有效位在任何时候被复位，则检测逻辑和内部挂起检测锁存器被置位，当内部挂起锁存器被设置并且保持有效时，激活允许正在进行中的请求完成并保持处于非活动状态的新请求的逻辑，直到检测到内部挂起的请求能够完成，从而重置内部挂起检测锁存器。

19. 发明申请

US20110320755A1 TRACKING DYNAMIC MEMORY REALLOCATION USING A SINGLE STORAGE ADDRESS CONFIGURATION TABLE 失效
标题翻译：使用单个存储地址配置表跟踪动态内存重新安装
公开(公告)号：US20110320755A1
公开(公告)日：2011-12-29
申请号：US12821986
申请日：2010-06-23
申请人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
发明人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
IPC分类号： G06F12/06
CPC分类号： G06F12/0292
摘要： Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.
摘要翻译：使用具有第一寄存器和第二寄存器的单个配置表来跟踪动态存储器去分配包括将第一寄存器设置为活动寄存器，启动从存储器分区的期望存储增量的去分配，在第二寄存器中设置存储增量注册为无效，清除与单个配置表相关联的所有高速缓存，将第二个寄存器设置为活动寄存器，将第一个寄存器设置为非活动寄存器，将第一个寄存器中的所需存储增量设置为无效，将活动寄存器从第二个注册到第一个寄存器，使用单个配置表完成内存取消分配。

20. 发明申请

US20090210629A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SELECTIVELY PURGING CACHE ENTRIES 审中-公开
标题翻译：方法，系统和计算机程序产品，用于选择高速缓存进入
公开(公告)号：US20090210629A1
公开(公告)日：2009-08-20
申请号：US12032058
申请日：2008-02-15
申请人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
发明人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A method, system and computer program product for selectively purging entries in a cache of a computer system. The method includes determining a starting storage address and a length of the storage address range to be purged, determining preset values for a congruence class and a compartment of a cache directory, accessing the cache directory based on the preset value of the congruence class, and selecting an entry in the cache directory based on the preset value of the compartment, determining validity of the entry accessed by examining an ownership tag of the entry, comparing a line address of the entry with the starting storage address and a sum of the starting storage address and the length of the storage address range, and selectively purging the entry based on the comparison result.
摘要翻译：一种用于选择性地清除计算机系统的高速缓存中的条目的方法，系统和计算机程序产品。该方法包括确定要清除的存储地址范围的起始存储地址和长度，确定高速缓存目录的同余类和隔间的预设值，基于同余类的预设值访问高速缓存目录;以及基于所述隔室的所述预设值来选择所述缓存目录中的条目，通过检查所述条目的所有权标签来确定所访问的条目的有效性，将所述条目的行地址与所述起始存储地址进行比较，以及所述起始存储器地址和存储地址范围的长度，并且基于比较结果选择性地清除条目。

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