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11. 发明授权

US07627836B2 OPC trimming for performance 失效
标题翻译： OPC修剪性能
公开(公告)号：US07627836B2
公开(公告)日：2009-12-01
申请号：US11164044
申请日：2005-11-08
申请人： James A. Culp , Lars W. Liebmann , Rajeev Malik , K. Paul Muller , Shreesh Narasimha , Stephen L. Runyon , Patrick M. Williams
发明人： James A. Culp , Lars W. Liebmann , Rajeev Malik , K. Paul Muller , Shreesh Narasimha , Stephen L. Runyon , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.
摘要翻译：基于使用光学邻近校正技术的方法，在芯片制造之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。标记形状识别构成关键定时路径中的装置的电路的预定子组。根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。使用OPC技术为所选的关键设备制作掩码。

12. 发明授权

US07087477B2 FinFET SRAM cell using low mobility plane for cell stability and method for forming 失效
标题翻译： FinFET SRAM单元使用低迁移率平面进行电池稳定性和成型方法
公开(公告)号：US07087477B2
公开(公告)日：2006-08-08
申请号：US10987532
申请日：2004-11-12
申请人： David M. Fried , Randy W. Mann , K. Paul Muller , Edward J. Nowak
发明人： David M. Fried , Randy W. Mann , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L21/8238
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1203 , H01L29/785 , Y10S257/903
摘要： The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.
摘要翻译：本发明提供了一种用于形成它的器件设计和方法，其导致Fin场效应晶体管具有不同的增益而不会不利地影响器件密度。本发明在低载流子迁移率平面中形成相对较低的增益FinFET晶体管，并在高载流子迁移率平面内形成相对较高的增益FinFET晶体管。如此形成的，在高迁移率平面中形成的FinFET具有比在低迁移率平面中形成的FinFET更高的增益。这些实施例特别适用于静态随机存取存储器（SRAM）单元的设计和制造。在这种应用中，用作转移装置的n型FinFET的主体沿{110}平面形成。用作存储锁存器的n型FinFET和p型FinFET的主体沿{100}形成。如此形成的，传送装置的增益大约是n型存储锁存装置的增益的一半，有利于适当的SRAM操作。

13. 发明授权

US06537418B1 Spatially uniform gas supply and pump configuration for large wafer diameters 失效
标题翻译：空间均匀的气体供应和泵配置用于大晶圆直径
公开(公告)号：US06537418B1
公开(公告)日：2003-03-25
申请号：US08934101
申请日：1997-09-19
申请人： K. Paul Muller , Bertrand Flietner , Klaus Roithner
发明人： K. Paul Muller , Bertrand Flietner , Klaus Roithner
IPC分类号： H01L213065
CPC分类号： H01J37/32834 , H01J37/3244
摘要： A gas distribution plate (60) for a semiconductor processing chamber (86) includes a gas distribution plate for distributing gases across a surface of a semiconductor wafer (84) to be processed in the chamber. The gas distribution plates has a substantially planar member having gas outlets for distributing a reactant gas across the surface of the semiconductor wafer, the gas outlet means includes a plurality of apertures (66) defined in said planar member, the plurality of apertures having different areas at predetermined locations to adjust etching gas flow. A pump (80) is provided for evacuating a reactant-product gas created across the surface of the semiconductor wafer during wafer processing. The pump (80) includes a plurality of tubes extending through the planar member, the plurality of tubes having apertures, and the apertures have different areas at predetermined locations to adjust reactant gas and reactant-product gas flow wherein the gas outlets and the pump coact to substantially maintain a predetermined concentration of the reactant gas and a predetermined concentration of the reactant-product gas across the surface of the semiconductor wafer during wafer processing.
摘要翻译：一种用于半导体处理室（86）的气体分配板（60）包括用于在室内分配待处理半导体晶片（84）的表面的气体分配板。气体分配板具有基本平坦的构件，其具有用于在半导体晶片的表面上分布反应气体的气体出口，气体出口装置包括限定在所述平面构件中的多个孔（66），所述多个孔具有不同的区域在预定位置调节蚀刻气流。提供泵（80），用于在晶片处理期间排出在半导体晶片的表面上产生的反应物产物气体。泵（80）包括延伸穿过平面构件的多个管，多个管具有孔，并且孔在预定位置处具有不同的区域以调节反应气体和反应物产物气流，其中气体出口和泵共同以在晶片处理期间基本上保持预定浓度的反应气体和预定浓度的反应产物气体跨过半导体晶片的表面。

14. 发明授权

US06432754B1 Double SOI device with recess etch and epitaxy 失效
标题翻译：具有凹陷蚀刻和外延的双重SOI器件
公开(公告)号：US06432754B1
公开(公告)日：2002-08-13
申请号：US09788979
申请日：2001-02-20
申请人： Fariborz Assaderaghi , Tze-Chiang Chen , K. Paul Muller , Edward Joseph Nowak , Devendra Kumar Sadana , Ghavam G. Shahidi
发明人： Fariborz Assaderaghi , Tze-Chiang Chen , K. Paul Muller , Edward Joseph Nowak , Devendra Kumar Sadana , Ghavam G. Shahidi
IPC分类号： H01L2100
CPC分类号： H01L29/78696 , H01L29/41733 , H01L29/66772 , H01L29/78603 , H01L29/78618
摘要： The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.
摘要翻译：本发明提供了用于形成接地平面SOI器件的各种方法，该器件至少包括形成在绝缘体上硅（SOI）晶片的顶部含Si表面上的场效应晶体管; 以及位于场效应晶体管下方的氧化物区域，位于形成在所述SOI晶片中的源极和漏极区域之间的区域中，所述氧化物区域与所述SOI晶片中形成的浅延伸区对接，并且与所述源极侧向相邻，漏区。

15. 发明授权

US06291353B1 Lateral patterning 失效
标题翻译：横向图案
公开(公告)号：US06291353B1
公开(公告)日：2001-09-18
申请号：US09377246
申请日：1999-08-19
申请人： K. Paul Muller , Hon-Sum P. Wong
发明人： K. Paul Muller , Hon-Sum P. Wong
IPC分类号： H01L2176
CPC分类号： H01L27/1087 , H01L21/3083 , H01L21/3086 , H01L21/76232 , H01L27/10876 , H01L29/1037 , H01L29/66181 , H01L29/66666 , H01L29/7827
摘要： A method and structure for forming an integrated circuit chip having at least one opening in a substrate includes forming an opening having vertical walls in the substrate, protecting a first portion of the vertical walls of the opening, leaving a second portion of the vertical walls unprotected, and laterally patterning the second portion of the opening to change a shape or property of the opening.
摘要翻译：用于形成在衬底中具有至少一个开口的集成电路芯片的方法和结构包括在衬底中形成具有垂直壁的开口，保护开口的垂直壁的第一部分，留下不受保护的垂直壁的第二部分并且横向地图案化开口的第二部分以改变开口的形状或性质。

16. 发明授权

US5877061A Methods for roughening and volume expansion of trench sidewalls to form high capacitance trench cell for high density dram applications 失效
标题翻译：沟槽侧壁的粗化和体积膨胀的方法，以形成用于高密度电镀应用的高电容沟槽电池
公开(公告)号：US5877061A
公开(公告)日：1999-03-02
申请号：US807479
申请日：1997-02-25
申请人： Scott D. Halle , ChorngLii Hwang , K. Paul Muller
发明人： Scott D. Halle , ChorngLii Hwang , K. Paul Muller
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/82 , H01L27/10861 , H01L28/84 , Y10S438/964
摘要： Trench cells with increased storage capacity are prepared with roughened sidewalls using a layer of grainy polysilicon or hemispherical grain polysilicon. The top collar region of the trench is protected with oxide while the lower portion of the trench coated with polysilicon or hemispherical grain polysilicon is etched isotropically. The trench structure created has roughened sidewalls for increased volume of storage.
摘要翻译：具有增加存储容量的沟槽电池使用粒状多晶硅层或半球形晶粒多晶硅的粗糙化侧壁制备。沟槽的顶环区域被氧化物保护，而多晶硅或半球状晶粒多晶硅的沟槽的下部被各向同性地蚀刻。所形成的沟槽结构使得侧壁变粗糙以增加存储容积。

17. 发明申请

US20130181738A1 SOFT ERROR RESILIENT FPGA 失效
公开(公告)号：US20130181738A1
公开(公告)日：2013-07-18
申请号：US13352900
申请日：2012-01-18
申请人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
发明人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H03K19/17764
摘要： A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

18. 发明授权

US07361959B2 CMOS circuits including a passive element having a low end resistance 有权
标题翻译： CMOS电路包括具有低端电阻的无源元件
公开(公告)号：US07361959B2
公开(公告)日：2008-04-22
申请号：US11164515
申请日：2005-11-28
申请人： Christopher D. Sheraw , Alyssa C. Bonnoit , K. Paul Muller , Werner Rausch
发明人： Christopher D. Sheraw , Alyssa C. Bonnoit , K. Paul Muller , Werner Rausch
IPC分类号： H01L29/76
CPC分类号： H01L27/0629 , H01L21/26506 , H01L28/20 , H01L28/40 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，以及用于形成这种CMOS电路的方法。更具体地说，本发明涉及包含诸如埋地电阻器，电容器，二极管，电感器，衰减器，功率分配器和天线等无源元件的CMOS电路，其特征在于端接触电阻小于90欧姆微量元素这样的低端电阻可以通过将无源元件的间隔物宽度减小到约10nm至约30nm的范围，或通过在预非晶化注入步骤期间掩蔽无源元件来实现，使得无源元件基本上没有前非晶化植入物。

19. 发明授权

US06967351B2 Finfet SRAM cell using low mobility plane for cell stability and method for forming 有权
标题翻译： Finfet SRAM单元使用低迁移率平面进行电池稳定性和形成方法
公开(公告)号：US06967351B2
公开(公告)日：2005-11-22
申请号：US10011351
申请日：2001-12-04
申请人： David M. Fried , Randy W. Mann , K. Paul Muller , Edward J. Nowak
发明人： David M. Fried , Randy W. Mann , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/12 , H01L29/04
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1203 , H01L29/785 , Y10S257/903
摘要： The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.
摘要翻译：本发明提供了一种用于形成它的器件设计和方法，其导致Fin场效应晶体管具有不同的增益而不会不利地影响器件密度。本发明在低载流子迁移率平面中形成相对较低的增益FinFET晶体管，并在高载流子迁移率平面内形成相对较高的增益FinFET晶体管。如此形成的，在高迁移率平面中形成的FinFET具有比在低迁移率平面中形成的FinFET更高的增益。这些实施例特别适用于静态随机存取存储器（SRAM）单元的设计和制造。在这种应用中，用作转移装置的n型FinFET的主体沿{110}平面形成。用作存储锁存器的n型FinFET和p型FinFET的主体沿{100}形成。如此形成的，传送装置的增益大约是n型存储锁存装置的增益的一半，有利于适当的SRAM操作。

20. 发明授权

US06913960B2 Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication 失效
标题翻译：基于鳍的双重多晶硅动态阈值CMOS FET与间隔栅极和制造方法
公开(公告)号：US06913960B2
公开(公告)日：2005-07-05
申请号：US10843029
申请日：2004-05-11
申请人： Andres Bryant , K. Paul Muller , Edward J. Nowak
发明人： Andres Bryant , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L21/28 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/78 , H01L29/786 , H01L21/8238
CPC分类号： H01L29/785 , H01L21/2815 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795 , H01L29/783
摘要： The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-source/drain capacitance. The low body-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.
摘要翻译：本发明提供一种动态阈值（DT）CMOS FET及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供一种DT CMOS FET，其在栅极和主体之间具有短的低电阻连接，并且具有低的体源/漏极电容。低体积/漏极电容使用薄的翅片型体实现。栅极和体接触之间的低电阻连接是通过使栅极和主体接触在翅片的相对的长边上对准来实现的，桥与电极连接门和主体的窄鳍的顶部之间形成一个桥。

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