专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08513972B2 Soft error resilient FPGA 失效
公开(公告)号：US08513972B2
公开(公告)日：2013-08-20
申请号：US13352900
申请日：2012-01-18
申请人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
发明人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H03K19/17764
摘要： A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

2. 发明申请

US20130181738A1 SOFT ERROR RESILIENT FPGA 失效
公开(公告)号：US20130181738A1
公开(公告)日：2013-07-18
申请号：US13352900
申请日：2012-01-18
申请人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
发明人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H03K19/17764
摘要： A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

3. 发明授权

US08806177B2 Prefetch engine based translation prefetching 有权
标题翻译：预取引擎基于翻译预取
公开(公告)号：US08806177B2
公开(公告)日：2014-08-12
申请号：US11482222
申请日：2006-07-07
申请人： Orran Y. Krieger , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0862 , G06F2212/6028 , G06F2212/651 , G06F2212/654
摘要： A method and system for prefetching in computer system are provided. The method in one aspect includes using a prefetch engine to perform prefetch instructions and to translate unmapped data. Misses to address translations during the prefetch are handled and resolved. The method also includes storing the resolved translations in a respective cache translation table. A system for prefetching in one aspect includes a prefetch engine operable to receive instructions to prefetch data from the main memory. The prefetch engine is also operable to search cache address translation for prefetch data and perform address mapping translation, if the prefetch data is unmapped. The prefetch engine is further operable to prefetch the data and store the address mapping in one or more cache memory, if the data is unmapped.
摘要翻译：提供了一种在计算机系统中预取的方法和系统。该方法在一个方面包括使用预取引擎来执行预取指令并转换未映射的数据。在预取期间解决翻译错误的处理和解决。该方法还包括将分辨的翻译存储在相应的缓存转换表中。用于在一个方面预取的系统包括预取引擎，其可操作以接收从主存储器预取数据的指令。如果预取数据未被映射，则预取引擎还可用于搜索缓存地址转换以获取预取数据并执行地址映射转换。如果数据未被映射，则预取引擎还可操作以预取数据并将地址映射存储在一个或多个高速缓冲存储器中。

4. 发明授权

US08674856B2 Data compression utilizing longest common subsequence template 失效
标题翻译：使用最长公共子序列模板的数据压缩
公开(公告)号：US08674856B2
公开(公告)日：2014-03-18
申请号：US13587669
申请日：2012-08-16
申请人： Kanak B. Agarwal , Damir A. Jamsek , Michael A. Paolini , Robert B. Tremaine
发明人： Kanak B. Agarwal , Damir A. Jamsek , Michael A. Paolini , Robert B. Tremaine
IPC分类号： H03M7/34
CPC分类号： H03M7/30 , H03M7/607
摘要： In response to receipt of an input string, an attempt is made to identify, in a template store, a closely matching template for use as a compression template. In response to identification of a closely matching template that can be used as a compression template, the input string is compressed into a compressed string by reference to a longest common subsequence compression template. Compressing the input string includes encoding, in a compressed string, an identifier of the compression template, encoding substrings of the input string not having commonality with the compression template of at least a predetermined length as literals, and encoding substrings of the input string having commonality with the compression template of at least the predetermined length as a jump distance without reference to a base location in the compression template. The compressed string is then output.
摘要翻译：响应于输入字符串的接收，尝试在模板存储器中识别紧密匹配的模板以用作压缩模板。响应于可以用作压缩模板的紧密匹配的模板的识别，通过参考最长的公共子序列压缩模板将输入字符串压缩成压缩字符串。压缩输入字符串包括在压缩字符串中编码压缩模板的标识符，将与压缩模板具有至少预定长度的压缩模板不一致的输入字符串的子串编码为文字，以及编码具有共同性的输入字符串的子串至少具有预定长度的压缩模板作为跳跃距离，而不参考压缩模板中的基本位置。然后输出压缩字符串。

5. 发明申请

US20120023300A1 MEMORY PAGE MANAGEMENT IN A TIERED MEMORY SYSTEM 有权
标题翻译：一个层次化的记忆系统中的存储页面管理
公开(公告)号：US20120023300A1
公开(公告)日：2012-01-26
申请号：US12843718
申请日：2010-07-26
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/16 , G06F12/14
CPC分类号： G06F12/1009 , G06F11/3471 , G06F12/1475 , G06F2201/88
摘要： Memory page management in a tiered memory system including a system that includes at least one page table for storing a plurality of entries, each entry associated with a page of memory and each entry including an address of the page and a memory tier of the page. The system also includes a control program configured for allocating pages associated with the entries to a software module, the allocated pages from at least two different memory tiers. The system further includes an agent of the control program capable of operating independently of the control program, the agent configured for receiving an authorization key to the allocated pages, and for migrating the allocated pages between the different memory tiers responsive to the authorization key.
摘要翻译：包括包括至少一个用于存储多个条目的页表的系统的系统中的存储器页面管理，每个条目与存储器页面相关联，每个条目包括页面的地址和页面的存储器层。该系统还包括配置用于将与条目相关联的页面分配给软件模块的控制程序，来自至少两个不同存储器层的所分配的页面。该系统还包括能够独立于控制程序操作的控制程序的代理，被配置为接收对所分配的页面的授权密钥的代理，以及响应于授权密钥在不同存储器层之间迁移分配的页面。

6. 发明申请

US20110161597A1 Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller 审中-公开
标题翻译：组合内存包括通过IO控制器访问的存储内存中的逻辑分区
公开(公告)号：US20110161597A1
公开(公告)日：2011-06-30
申请号：US12649856
申请日：2009-12-30
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0895
摘要： A computer system having a combined memory. A first logical partition of the combined memory is a main memory region in a storage memory. A second logical partition of the combined memory is a direct memory region in a main memory. A memory controller comprising a storage controller is configured to receive a memory access request including a real address from a processor, determine whether the real address is for the first logical partition or for the second logical partition. If the address is for the first logical partition the storage controller communicates with an IO controller in the storage memory to service the memory access request. If the address is for the direct memory region, the memory controller services the memory access request in a conventional manner.
摘要翻译：具有组合存储器的计算机系统。组合存储器的第一逻辑分区是存储存储器中的主存储器区域。组合存储器的第二逻辑分区是主存储器中的直接存储器区域。包括存储控制器的存储器控制器被配置为从处理器接收包括实际地址的存储器访问请求，确定实际地址是为第一逻辑分区还是用于第二逻辑分区。如果地址是用于第一逻辑分区，则存储控制器与存储器中的IO控制器通信以服务存储器访问请求。如果地址用于直接存储区域，则存储器控制器以常规方式服务存储器访问请求。

7. 发明申请

US20110087834A1 Memory Package Utilizing At Least Two Types of Memories 有权
标题翻译：记忆包利用至少两种类型的记忆
公开(公告)号：US20110087834A1
公开(公告)日：2011-04-14
申请号：US12576028
申请日：2009-10-08
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/16 , G06F12/02
CPC分类号： G06F12/0638 , Y10S707/99931
摘要： A memory system and methods for memory manage are presented. The memory system includes a volatile memory electrically connected to a high-density memory; a memory controller that expects data to be written or read to or from the memory system at a bandwidth and a latency associated with the volatile memory; a directory within the volatile memory that associates a volatile memory address with data stored in the high-density memory; and redundant storage in the high-density memory that stores a copy of the association between the volatile memory address and the data stored in the high-density memory. The methods for memory management allow writing to and reading from the memory system using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).
摘要翻译：介绍了一种存储器系统和存储器管理方法。存储器系统包括电连接到高密度存储器的易失性存储器; 期望以与易失性存储器相关联的带宽和等待时间从存储器系统写入或读取数据的存储器控制器; 易失性存储器内的目录，其将易失性存储器地址与存储在高密度存储器中的数据相关联; 以及高密度存储器中的冗余存储器，其存储易失性存储器地址和存储在高密度存储器中的数据之间的关联的副本。用于存储器管理的方法允许使用第一存储器读/写接口（例如DRAM接口等）从存储器系统进行写入和读取，尽管数据存储在不同存储器类型（例如FLASH等）的器件中，。

8. 发明申请

US20110075740A1 Configurable Differential to Single Ended IO 有权
标题翻译：可配置差分至单端IO
公开(公告)号：US20110075740A1
公开(公告)日：2011-03-31
申请号：US12568765
申请日：2009-09-29
申请人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
发明人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： H04B3/00
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译：一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。传输幅度和数据的单端或差分传输是功率模式的例子。控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。

9. 发明申请

US20100005218A1 ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM 审中-公开
标题翻译：增强的CASCADE互连存储系统
公开(公告)号：US20100005218A1
公开(公告)日：2010-01-07
申请号：US12165816
申请日：2008-07-01
申请人： Kevin C. Gower , Paul W. Coteus , Warren E. Maule , Robert B. Tremaine
发明人： Kevin C. Gower , Paul W. Coteus , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F12/06
CPC分类号： G06F13/4234
摘要： A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames.
摘要翻译：提供了一种用于提供增强级联互连存储器系统的系统，存储器集线器设备，方法和设计结构。该系统包括存储器控制器，存储器通道，耦合到存储器通道的存储器集线器设备，以经由另一个存储器集线器设备的直接连接和级联互连中的一个与存储器控制器进行通信，以及与存储控制器通信的多个存储器设备存储器控制器经由一个或多个级联互连的存储器集线器设备。存储器通道包括耦合到存储器控制器并且可操作用于传输可配置数据帧的单向下游链路段。存储器通道还包括耦合到存储器控制器并且可操作用于传送数据帧的单向上游链路段。

10. 发明授权

US07636813B2 Systems and methods for providing remote pre-fetch buffers 有权
标题翻译：用于提供远程预取缓冲区的系统和方法
公开(公告)号：US07636813B2
公开(公告)日：2009-12-22
申请号：US11419586
申请日：2006-05-22
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F13/18 , G06F13/374
CPC分类号： G06F13/1673
摘要： Systems and methods for providing remote pre-fetch buffers. The systems include a computer memory system with a memory controller, one or more memory busses connected to the memory controller, and at least one memory subsystem in communication with the memory controller via the memory busses. The memory controller generates, receives and responds to memory access requests including unsolicited data transfers. The memory subsystem includes one or more memory devices and logic to initiate an unsolicited data transfer to the memory controller based on analysis performed at the memory subsystem of prior memory access requests received by the memory subsystem.
摘要翻译：用于提供远程预取缓冲区的系统和方法。这些系统包括具有存储器控制器的计算机存储器系统，连接到存储器控制器的一个或多个存储器总线以及经由存储器总线与存储器控制器通信的至少一个存储器子系统。存储器控制器生成，接收并响应包括主动请求的数据传输的存储器访问请求。存储器子系统包括一个或多个存储器设备和逻辑，用于基于在存储器子系统处对由存储器子系统接收的先前存储器访问请求执行的分析来发起向存储器控制器的非请求数据传输。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式