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1. 发明授权

US06432754B1 Double SOI device with recess etch and epitaxy 失效
标题翻译：具有凹陷蚀刻和外延的双重SOI器件
公开(公告)号：US06432754B1
公开(公告)日：2002-08-13
申请号：US09788979
申请日：2001-02-20
申请人： Fariborz Assaderaghi , Tze-Chiang Chen , K. Paul Muller , Edward Joseph Nowak , Devendra Kumar Sadana , Ghavam G. Shahidi
发明人： Fariborz Assaderaghi , Tze-Chiang Chen , K. Paul Muller , Edward Joseph Nowak , Devendra Kumar Sadana , Ghavam G. Shahidi
IPC分类号： H01L2100
CPC分类号： H01L29/78696 , H01L29/41733 , H01L29/66772 , H01L29/78603 , H01L29/78618
摘要： The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.
摘要翻译：本发明提供了用于形成接地平面SOI器件的各种方法，该器件至少包括形成在绝缘体上硅（SOI）晶片的顶部含Si表面上的场效应晶体管; 以及位于场效应晶体管下方的氧化物区域，位于形成在所述SOI晶片中的源极和漏极区域之间的区域中，所述氧化物区域与所述SOI晶片中形成的浅延伸区对接，并且与所述源极侧向相邻，漏区。

2. 发明授权

US06333532B1 Patterned SOI regions in semiconductor chips 有权
标题翻译：半导体芯片中的图案化SOI区域
公开(公告)号：US06333532B1
公开(公告)日：2001-12-25
申请号：US09356295
申请日：1999-07-16
申请人： Bijan Davari , Devendra Kumar Sadana , Ghavam G. Shahidi , Sandip Tiwari
发明人： Bijan Davari , Devendra Kumar Sadana , Ghavam G. Shahidi , Sandip Tiwari
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L21/26533 , H01L21/266 , H01L21/76243 , H01L21/76264 , H01L21/76267 , H01L21/76286 , H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/945 , Y10S257/904
摘要： A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep trench in bulk Si while forming merged logic regions on SOI.
摘要翻译：描述了用于形成图案化SOI区域和体积区域的方法和结构，其中绝缘体上的含硅层可以具有多个选定的厚度，并且其中体积区域可适于形成DRAM，并且SOI区域可适合于形成合并逻辑如CMOS。氧离子注入用于在所选择的深度处形成图案化的掩埋氧化物层，并且掩模边缘可被成形为从一个深度到另一个深度形成阶梯状氧化物区域。可以通过掩埋氧化物端部区域形成沟槽，以去除含有单晶硅的衬底中的高浓度位错。本发明克服了在形成SOI上的合并逻辑区域的同时形成具有在体Si中的深沟槽的存储电容器形成DRAM的问题。

3. 发明授权

US07282425B2 Structure and method of integrating compound and elemental semiconductors for high-performance CMOS 失效
标题翻译：化合物和元素半导体用于高性能CMOS的结构和方法
公开(公告)号：US07282425B2
公开(公告)日：2007-10-16
申请号：US11046912
申请日：2005-01-31
申请人： Steven John Koester , Devendra Kumar Sadana , Ghavam G. Shahidi
发明人： Steven John Koester , Devendra Kumar Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/823807 , H01L21/02002 , H01L21/76254 , H01L21/76256 , H01L21/8258 , H01L21/84 , H01L27/1203
摘要： A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.
摘要翻译：制造半导体衬底的方法包括在化合物半导体衬底上外延生长元素半导体层。绝缘层沉积在元素半导体层的顶部上，以形成第一衬底。第一衬底被晶片结合到单晶Si衬底上，使得绝缘层与单晶Si衬底结合。半导体器件包括单晶衬底和形成在单晶衬底上的电介质层。在介电层上形成半导体化合物，在半导体化合物附近形成与半导体化合物晶格匹配的元素半导体材料。

4. 发明授权

US07504311B2 Structure and method of integrating compound and elemental semiconductors for high-performance CMOS 有权
标题翻译：化合物和元素半导体用于高性能CMOS的结构和方法
公开(公告)号：US07504311B2
公开(公告)日：2009-03-17
申请号：US11762376
申请日：2007-06-13
申请人： Steven John Koester , Devendra Kumar Sadana , Ghavam G. Shahidi
发明人： Steven John Koester , Devendra Kumar Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/84
CPC分类号： H01L21/823807 , H01L21/02002 , H01L21/76254 , H01L21/76256 , H01L21/8258 , H01L21/84 , H01L27/1203
摘要： A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.
摘要翻译：制造半导体衬底的方法包括在化合物半导体衬底上外延生长元素半导体层。绝缘层沉积在元素半导体层的顶部上，以形成第一衬底。第一衬底被晶片结合到单晶Si衬底上，使得绝缘层与单晶Si衬底结合。半导体器件包括单晶衬底和形成在单晶衬底上的电介质层。在介电层上形成半导体化合物，在半导体化合物附近形成与半导体化合物晶格匹配的元素半导体材料。

5. 发明授权

US06756257B2 Patterned SOI regions on semiconductor chips 有权
标题翻译：半导体芯片上的图案化SOI区域
公开(公告)号：US06756257B2
公开(公告)日：2004-06-29
申请号：US09975435
申请日：2001-10-11
申请人： Bijan Davari , Devendra Kumar Sadana , Ghavam G. Shahidi , Sandip Tiwari
发明人： Bijan Davari , Devendra Kumar Sadana , Ghavam G. Shahidi , Sandip Tiwari
IPC分类号： H01L2100
CPC分类号： H01L27/10894 , H01L21/26533 , H01L21/266 , H01L21/76243 , H01L21/76264 , H01L21/76267 , H01L21/76286 , H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/945 , Y10S257/904
摘要： A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.
摘要翻译：描述了用于形成图案化SOI区域和体积区域的方法和结构，其中绝缘体上的含硅层可以具有多个选定的厚度，并且其中体积区域可适于形成DRAM，并且SOI区域可适合于形成合并逻辑如CMOS。氧离子注入用于在所选择的深度形成图案化的掩埋氧化物层，并且掩模边缘可被成形为从一个深度到另一个深度形成阶梯状氧化物区域。可以通过掩埋氧化物端部区域形成沟槽，以去除含有单晶硅的衬底中的高浓度位错。本发明克服了形成DRAM的存储电容器形成的体积为Si的深沟槽，同时在SOI上形成合并的逻辑区域的问题。

6. 发明授权

US6090689A Method of forming buried oxide layers in silicon 失效
标题翻译：在硅中形成掩埋氧化物层的方法
公开(公告)号：US6090689A
公开(公告)日：2000-07-18
申请号：US34445
申请日：1998-03-04
申请人： Devendra Kumar Sadana , Orin Wayne Holland
发明人： Devendra Kumar Sadana , Orin Wayne Holland
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76243
摘要： A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.
摘要翻译：描述了一种用于形成上绝缘体的方法，其包括以下步骤：在升高的温度下将氧离子注入到硅衬底中，以较低的剂量离子注入低于200℃的氧气以形成非晶硅层;以及退火步骤以单独形成有缺陷的单晶硅和多晶硅或多晶硅的混合物，然后形成来自非晶硅层的氧化硅，以在硅衬底的表面下方形成连续的氧化硅层，以提供分离的表面硅层。本发明克服了形成不连续掩埋氧化层的氧化硅的孤立孤岛的问题。

7. 发明授权

US6043166A Silicon-on-insulator substrates using low dose implantation 失效
标题翻译：使用低剂量注入的绝缘体上硅衬底
公开(公告)号：US6043166A
公开(公告)日：2000-03-28
申请号：US961131
申请日：1997-10-30
申请人： Peter Roitman , Devendra Kumar Sadana
发明人： Peter Roitman , Devendra Kumar Sadana
IPC分类号： H01L21/265 , H01L21/762
CPC分类号： H01L21/26533 , H01L21/76243
摘要： An SOI substrate and method of forming is described incorporating the steps of implanting oxygen under two conditions and performing two high temperature anneals at temperatures above 1250.degree. C. and above 1300.degree. C., respectively, at two respective oxygen concentrations. The invention overcomes the problem of high SOI substrate fabrication cost due to ion implant time and of getting high quality buried oxide (BOX) layers below a thin layer of single crystal silicon.
摘要翻译：描述SOI衬底和形成方法，其包括在两个条件下注入氧气的步骤，并且在两个相应的氧浓度下分别在高于1250℃和高于1300℃的温度下进行两个高温退火。本发明克服了由于离子注入时间导致的高SOI衬底制造成本以及在单晶硅薄层之下获得高质量埋藏氧化物（BOX）层的问题。

8. 发明授权

US5930643A Defect induced buried oxide (DIBOX) for throughput SOI 失效
标题翻译：缺陷诱导埋氧（DIBOX）用于吞吐量SOI
公开(公告)号：US5930643A
公开(公告)日：1999-07-27
申请号：US995585
申请日：1997-12-22
申请人： Devendra Kumar Sadana , Joel P. de Souza
发明人： Devendra Kumar Sadana , Joel P. de Souza
IPC分类号： H01L21/265 , H01L21/762
CPC分类号： H01L21/26533 , H01L21/76243
摘要： A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing a first low energy implantation step to create a stable defect region; a second low energy implantation step to create an amorphous layer adjacent to the stable defect region; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising said semiconductor substrate having said DIBOX is also provided herein.
摘要翻译：利用第一低能量注入步骤在半导体衬底中制造缺陷诱导的掩埋氧化物（DIBOX）区域以产生稳定的缺陷区域的方法; 第二低能量注入步骤，以产生邻近所述稳定缺陷区域的非晶层; 提供氧化和任选的退火。也提供了包含具有所述DIBOX的所述半导体衬底的绝缘体上硅（SOI）材料。

9. 发明授权

US07550369B2 Method for fabricating low-defect-density changed orientation Si 失效
标题翻译：制造低缺陷密度变化取向Si的方法
公开(公告)号：US07550369B2
公开(公告)日：2009-06-23
申请号：US11873928
申请日：2007-10-17
申请人： Joel Pereira de Souza , Keith Edward Fogel , John Albrecht Ott , Devendra Kumar Sadana , Katherine Lynn Saenger
发明人： Joel Pereira de Souza , Keith Edward Fogel , John Albrecht Ott , Devendra Kumar Sadana , Katherine Lynn Saenger
IPC分类号： H01L21/20
CPC分类号： H01L21/26506 , H01L21/2022
摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.
摘要翻译：本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向具有不同的方向。更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶非晶层的原始方向。本发明方法的关键部件是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以消除在初始再结晶退火之后残留的缺陷。本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

10. 发明授权

US07285473B2 Method for fabricating low-defect-density changed orientation Si 失效
标题翻译：制造低缺陷密度变化取向Si的方法
公开(公告)号：US07285473B2
公开(公告)日：2007-10-23
申请号：US11031142
申请日：2005-01-07
申请人： Joel Pereira de Souza , Keith Edward Fogel , John Albrecht Ott , Devendra Kumar Sadana , Katherine Lynn Saenger
发明人： Joel Pereira de Souza , Keith Edward Fogel , John Albrecht Ott , Devendra Kumar Sadana , Katherine Lynn Saenger
IPC分类号： H01L21/76
CPC分类号： H01L21/26506 , H01L21/2022
摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.
摘要翻译：本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向具有不同的方向。更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶非晶层的原始方向。本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

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