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11. 发明授权

US5015881A High speed decoding circuit with improved AND gate 失效
标题翻译：具有改进的与门的高速解码电路
公开(公告)号：US5015881A
公开(公告)日：1991-05-14
申请号：US488358
申请日：1990-03-02
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： G11C11/408 , G11C8/10 , H03K19/017 , H03K19/0948 , H03K19/20 , H03M7/22
CPC分类号： G11C8/10 , H03K19/0948 , H03M7/22
摘要： An AND gate includes first and second opposite-type field effect transistors, each including first and second conduction path terminals and a control electrode. The gate's output terminal is connected, in common, to the second conduction path terminals of the transistors. A first logic input is connected to the first conduction path terminal of the first transistor and a second logic input is connected in common to the control electrode of the first transistor and to the first conduction path terminal of the second transistor. A third logic input is applied to the control electrode of the second transistor. In a standby state prior to the application of logic signals all three logic inputs are in the same state. This assures no conduction of logic signals, while conditioning the gate for rapid selection when logic signals are applied. Subsequently, logic signals are applied to the inputs with the third input being the complement level of the logic signal on the first input. As a result, the circuit's output terminal only provides a high state output if the first and second inputs are in the high state. An erroneous output is avoided in the event of a skew of the inputs due to a clamping acton exerted on the gate's output by the first transistor. A logical decoding circuit using the above described AND circuit enables a one-out-of-32 decode to occur in three stages including a self-contained reset for fast cycle operation.

12. 发明授权

US4998028A High speed CMOS logic device for providing ECL compatible logic levels 失效
标题翻译：高速CMOS逻辑器件，用于提供ECL兼容的逻辑电平
公开(公告)号：US4998028A
公开(公告)日：1991-03-05
申请号：US471155
申请日：1990-01-26
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： H03K3/011 , H03K3/356 , H03K17/14 , H03K19/0185
CPC分类号： H03K3/011 , H03K17/145 , H03K19/018521 , H03K3/356113
摘要： CMOS ECL drive circuit for providing regulated ECL logic levels. A CMOS logic circuit is connected by parallel N channel and P channel devices to serially connected N and P channel devices. The serially connected N and P channel devices are connected across a CMOS power supply with gate connections connected to the logic circuit. The parallel devices provide a regulating feedback current to one of the serially connected P channel and N channel devices during each of first and second ECL logic states. The feedback current effectively controls the bias on the gate connections of the serially connected P and N channel devices. The voltage at the junction of the serially connected P and N channel devices is regulated by each of the parallel connected devices.

13. 发明授权

US4835419A Source-follower emitter-coupled-logic receiver circuit 失效
标题翻译：源极跟随器发射极耦合逻辑接收器电路
公开(公告)号：US4835419A
公开(公告)日：1989-05-30
申请号：US115690
申请日：1987-10-30
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： H03K5/02 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A circuit means for interfacing between small emitter-coupled-logic (ECL) circuit voltage levels and larger field effect transistor (FET) circuits voltage level. The circuit interface means includes a source-follower stage wherein a first transistor device is ratioed relative to a second transistor device, so that a high percentage of an input voltage level signal to the first transistor device appears at a node between the first and second transistor devices, having been level shifted downward by greater than or equal to an n-channel threshold voltage. The percentage is enhanced by applying the complement of the input voltage level signal to the gate of the second transistor device. A gain stage is connected to the source-follower stage and includes third and fourth transistor devices wherein gain is developed by applying the level shifted input signal to the source of the fourth transistor device and the complement of the input signal directly to the gate of the fourth transistor device. A compensation stage for the circuit may also be included.

14. 发明授权

US07821858B2 eDRAM hierarchical differential sense AMP 有权
标题翻译： eDRAM分层差分放大器
公开(公告)号：US07821858B2
公开(公告)日：2010-10-26
申请号：US12326143
申请日：2008-12-02
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C11/4097 , G11C11/4091
摘要： In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.
摘要翻译：在本发明的一个实施例中，实现了分级差分感测方法，其中1行DRAM单元的阵列以行和列组织，其中行表示字，并且列表示字的位，每个位列具有多于一个一对平衡的，真实的和补充的局部位线，局部位线通过CMOS晶体管开关连接到一对平衡的，真实的和补充的全局位线。

15. 发明授权

US07460423B2 Hierarchical 2T-DRAM with self-timed sensing 有权
标题翻译：具有自定时感测功能的分层2T-DRAM
公开(公告)号：US07460423B2
公开(公告)日：2008-12-02
申请号：US11620282
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C7/00 , G11C5/06 , G11C11/00
CPC分类号： G11C8/10 , G11C7/18 , G11C11/405 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2211/4013 , Y10T29/49002
摘要： An embodiment of the present invention is an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.
摘要翻译：本发明的实施例是以行和列组织的2个晶体管DRAM单元的阵列，其中行表示字和列表示字的位，每个位列具有一对平衡的，真和补码位线，该位线路以分层位线结构连接，包括至少一个本地位线对和一个全局位线对，连接到全局位线对的感测电路在读取访问期间检测任一行上的差分电压转换，并提供一个感应选通信号。

16. 发明授权

US07460387B2 eDRAM hierarchical differential sense amp 失效
标题翻译： eDRAM分层差分放大器
公开(公告)号：US07460387B2
公开(公告)日：2008-12-02
申请号：US11620328
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C5/06 , G11C11/24 , G11C7/00
CPC分类号： G11C11/4097 , G11C11/4091
摘要： In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.
摘要翻译：在本发明的一个实施例中，实现了分级差分感测方法，其中1行DRAM单元的阵列以行和列组织，其中行表示字，并且列表示字的位，每个位列具有多于一个一对平衡的，真实的和补充的局部位线，局部位线通过CMOS晶体管开关连接到一对平衡的，真实的和补充的全局位线。

17. 发明申请

US20080165561A1 HIERARCHICAL SIX-TRANSISTOR SRAM 有权
标题翻译：分层六极晶体管SRAM
公开(公告)号：US20080165561A1
公开(公告)日：2008-07-10
申请号：US11620297
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C5/06
CPC分类号： G11C11/412 , G11C11/413
摘要： An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing six devices, the storage nodes which store the true and complement of the data are constructed from a four device, cross coupled flip-flop cell, wherein one internal storage node of this cell is connected through an access pass gate to one local bit line (LBL), the second internal storage node connected in a like manner to a second LBL, each LBL connected to a limited number, e.g. 8 to 32 of other similar storage cells, the two LBLs each connected to the gate of a separate read head nFET for discharging to ground one of two previously precharged global read lines so as to pass the inverse of the signal on the LBL and thus on the read head gate to a global read/write bit line.
摘要翻译：本发明的实施例是一种SRAM存储器阵列，其包括具有每个单元包含六个器件的存储器单元，存储数据的真实和补码的存储节点由四个器件交叉耦合的触发器单元构成，其中一个内部该单元的存储节点通过访问传递门连接到一个本地位线（LBL），第二内部存储节点以类似的方式连接到第二LBL，每个LBL连接到有限数量，例如 8到32个其他类似的存储单元，两个LBL各自连接到单独的读头nFET的栅极，用于将两个先前预充电的全局读取线之一放电到地之上，以便通过LBL上的信号的反相，从而导通读头到全局读/写位线。

18. 发明授权

US07065665B2 Interlocked synchronous pipeline clock gating 有权
公开(公告)号：US07065665B2
公开(公告)日：2006-06-20
申请号：US10262769
申请日：2002-10-02
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： H04L5/00 , G06F9/30
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

19. 发明授权

US07499312B2 Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line 失效
标题翻译：快速，稳定的SRAM单元使用七个器件和分级位/检测线
公开(公告)号：US07499312B2
公开(公告)日：2009-03-03
申请号：US11620316
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C11/00 , G11C5/06
CPC分类号： G11C11/412 , G11C11/413
摘要： An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing seven devices, wherein the basic storage nodes, which store the true and complement of the data, are constructed from six devices, forming a cross-coupled flip-flop cell. One internal storage node of this cell being connected to a separate read-pass device which passes the state of this node to a local bit line (LBL) for single-ended sensing, with the gate of this separate read-pass device connected to a separate read-word line.
摘要翻译：本发明的一个实施例是一种SRAM存储器阵列，其包括具有每个单元的存储器单元，所述存储器单元包含七个器件，其中存储数据的真实和补码的基本存储节点由六个器件构成，形成交叉耦合触发器，触发器电池。该单元的一个内部存储节点连接到单独的读通设备，该设备将该节点的状态传递到用于单端感测的本地位线（LBL），该单独的读通道设备的门连接到单独的读字线。

20. 发明申请

US20080165601A1 eDRAM HIERARCHICAL DIFFERENTIAL SENSE AMP 失效
标题翻译： eDRAM分层差分感测放大器
公开(公告)号：US20080165601A1
公开(公告)日：2008-07-10
申请号：US11620328
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C7/00
CPC分类号： G11C11/4097 , G11C11/4091
摘要： In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.
摘要翻译：在本发明的一个实施例中，实现了分级差分感测方法，其中1行DRAM单元的阵列以行和列组织，其中行表示字，并且列表示字的位，每个位列具有多于一个一对平衡的，真实的和补充的局部位线，局部位线通过CMOS晶体管开关连接到一对平衡的，真实的和补充的全局位线。

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