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1. 发明授权

US07499312B2 Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line 失效
标题翻译：快速，稳定的SRAM单元使用七个器件和分级位/检测线
公开(公告)号：US07499312B2
公开(公告)日：2009-03-03
申请号：US11620316
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C11/00 , G11C5/06
CPC分类号： G11C11/412 , G11C11/413
摘要： An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing seven devices, wherein the basic storage nodes, which store the true and complement of the data, are constructed from six devices, forming a cross-coupled flip-flop cell. One internal storage node of this cell being connected to a separate read-pass device which passes the state of this node to a local bit line (LBL) for single-ended sensing, with the gate of this separate read-pass device connected to a separate read-word line.
摘要翻译：本发明的一个实施例是一种SRAM存储器阵列，其包括具有每个单元的存储器单元，所述存储器单元包含七个器件，其中存储数据的真实和补码的基本存储节点由六个器件构成，形成交叉耦合触发器，触发器电池。该单元的一个内部存储节点连接到单独的读通设备，该设备将该节点的状态传递到用于单端感测的本地位线（LBL），该单独的读通道设备的门连接到单独的读字线。

2. 发明申请

US20080165601A1 eDRAM HIERARCHICAL DIFFERENTIAL SENSE AMP 失效
标题翻译： eDRAM分层差分感测放大器
公开(公告)号：US20080165601A1
公开(公告)日：2008-07-10
申请号：US11620328
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C7/00
CPC分类号： G11C11/4097 , G11C11/4091
摘要： In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.
摘要翻译：在本发明的一个实施例中，实现了分级差分感测方法，其中1行DRAM单元的阵列以行和列组织，其中行表示字，并且列表示字的位，每个位列具有多于一个一对平衡的，真实的和补充的局部位线，局部位线通过CMOS晶体管开关连接到一对平衡的，真实的和补充的全局位线。

3. 发明授权

US07709299B2 Hierarchical 2T-DRAM with self-timed sensing 失效
标题翻译：具有自定时感测功能的分层2T-DRAM
公开(公告)号：US07709299B2
公开(公告)日：2010-05-04
申请号：US12198969
申请日：2008-08-27
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： H01L21/82
CPC分类号： G11C8/10 , G11C7/18 , G11C11/405 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2211/4013 , Y10T29/49002
摘要： An embodiment of the present invention is method of forming an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.
摘要翻译：本发明的实施例是形成以行和列组织的2个晶体管DRAM单元的阵列的方法，其中行表示字和列表示字的位，每个位列具有一对平衡的，真和补码位线位线以分层位线结构连接，包括至少一个本地位线对和一个全局位线对，连接到全局位线对的感测电路在读取访问期间检测任一行上的差分电压转换并提供感测选通信号。

4. 发明授权

US07471546B2 Hierarchical six-transistor SRAM 有权
标题翻译：分层六晶体管SRAM
公开(公告)号：US07471546B2
公开(公告)日：2008-12-30
申请号：US11620297
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing six devices, the storage nodes which store the true and complement of the data are constructed from a four device, cross coupled flip-flop cell, wherein one internal storage node of this cell is connected through an access pass gate to one local bit line (LBL), the second internal storage node connected in a like manner to a second LBL, each LBL connected to a limited number, e.g. 8 to 32 of other similar storage cells, the two LBLs each connected to the gate of a separate read head nFET for discharging to ground one of two previously precharged global read lines so as to pass the inverse of the signal on the LBL and thus on the read head gate to a global read/write bit line.
摘要翻译：本发明的实施例是一种SRAM存储器阵列，其包括具有每个单元包含六个器件的存储器单元，存储数据的真实和补码的存储节点由四个器件交叉耦合的触发器单元构成，其中一个内部该单元的存储节点通过访问传递门连接到一个本地位线（LBL），第二内部存储节点以类似的方式连接到第二LBL，每个LBL连接到有限数量，例如 8到32个其他类似的存储单元，两个LBL各自连接到单独的读头nFET的栅极，用于将两个先前预充电的全局读取线之一放电到地之上，以便通过LBL上的信号的反相，从而导通读头到全局读/写位线。

5. 发明申请

US20090080230A1 eDRAM Hierarchical Differential Sense AMP 有权
标题翻译： eDRAM分层差分感测AMP
公开(公告)号：US20090080230A1
公开(公告)日：2009-03-26
申请号：US12326143
申请日：2008-12-02
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C5/06 , G11C7/00 , G11C7/06 , G11C11/24
CPC分类号： G11C11/4097 , G11C11/4091
摘要： In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.
摘要翻译：在本发明的一个实施例中，实现了分级差分感测方法，其中1行DRAM单元的阵列以行和列组织，其中行表示字，并且列表示字的位，每个位列具有多于一个一对平衡的，真实的和补充的局部位线，局部位线通过CMOS晶体管开关连接到一对平衡的，真实的和补充的全局位线。

6. 发明申请

US20080308941A1 HIERARCHICAL 2T-DRAM WITH SELF-TIMED SENSING 失效
标题翻译：具有自定义感应的分层2T- DRAM
公开(公告)号：US20080308941A1
公开(公告)日：2008-12-18
申请号：US12198969
申请日：2008-08-27
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： H01S4/00
CPC分类号： G11C8/10 , G11C7/18 , G11C11/405 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2211/4013 , Y10T29/49002
摘要： An embodiment of the present invention is method of forming an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.
摘要翻译：本发明的实施例是形成以行和列组织的2个晶体管DRAM单元的阵列的方法，其中行表示字和列表示字的位，每个位列具有一对平衡的，真和补码位线位线以分层位线结构连接，包括至少一个本地位线对和一个全局位线对，连接到全局位线对的感测电路在读取访问期间检测任一行上的差分电压转换并提供感测选通信号。

7. 发明申请

US20080270683A1 SYSTEMS AND METHODS FOR A DRAM CONCURRENT REFRESH ENGINE WITH PROCESSOR INTERFACE 审中-公开
标题翻译：具有处理器接口的DRAM同时燃烧发动机的系统和方法
公开(公告)号：US20080270683A1
公开(公告)日：2008-10-30
申请号：US11739899
申请日：2007-04-25
申请人： John E. Barth , Richard E. Matick , Stanley E. Schuster
发明人： John E. Barth , Richard E. Matick , Stanley E. Schuster
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Systems and methods for a DRAM concurrent refresh engine with processor interface. In exemplary embodiments, memory cells requiring periodic refresh at least once each for a specified refresh interval and words of an array organized banks in which the banks are selected for access by a bank-enable signal, each bank having a word decoder accepting one of two refresh word addresses, one refresh word address for a normal access, and the other for a refresh access, one of the word addresses selected by two separate enable signals, provided by on-macro refresh logic, which includes instructions to select one bank for refresh when no normal access occurs and select one bank for refresh concurrently with a normal access having no bank conflicts, the refresh logic maintaining the refresh status, timing of the refresh interval, and insuring all memory cells are refreshed within the refresh interval.
摘要翻译：具有处理器接口的DRAM并发刷新引擎的系统和方法。在示例性实施例中，需要对于指定的刷新间隔至少每次刷新一次的存储器单元以及阵列组合的存储体的组，其中通过存储体使能信号选择存储体以进行存取，每个存储体具有接受两个刷新字地址，用于正常访问的一个刷新字地址，另一个用于刷新访问，由宏宏刷新逻辑提供的由两个单独使能信号选择的字地址之一，其包括选择一个银行刷新的指令当没有正常访问时，并且在没有存在冲突的正常访问的情况下同时选择一个存储体进行刷新，保持刷新状态的刷新逻辑，刷新间隔的定时以及保证所有存储单元在刷新间隔内被刷新。

8. 发明申请

US20080165560A1 Hierarchical 2T-DRAM with Self-Timed Sensing 有权
标题翻译：具有自定时感测的分层2T-DRAM
公开(公告)号：US20080165560A1
公开(公告)日：2008-07-10
申请号：US11620282
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C5/06
CPC分类号： G11C8/10 , G11C7/18 , G11C11/405 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2211/4013 , Y10T29/49002
摘要： An embodiment of the present invention is an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.
摘要翻译：本发明的实施例是以行和列组织的2个晶体管DRAM单元的阵列，其中行表示字和列表示字的位，每个位列具有一对平衡的，真和补码位线，该位线路以分层位线结构连接，包括至少一个本地位线对和一个全局位线对，连接到全局位线对的感测电路在读取访问期间检测任一行上的差分电压转换，并提供一个感应选通信号。

9. 发明申请

US20080165562A1 FAST, STABLE, SRAM CELL USING SEVEN DEVICES AND HIERARCHICAL BIT/SENSE LINE 失效
标题翻译：快速，稳定，使用七个器件和分层位/ SENSE线的SRAM单元
公开(公告)号：US20080165562A1
公开(公告)日：2008-07-10
申请号：US11620316
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C5/06
CPC分类号： G11C11/412 , G11C11/413
摘要： An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing seven devices, wherein the basic storage nodes, which store the true and complement of the data, are constructed from six devices, forming a cross-coupled flip-flop cell. One internal storage node of this cell being connected to a separate read-pass device which passes the state of this node to a local bit line (LBL) for single-ended sensing, with the gate of this separate read-pass device connected to a separate read-word line.
摘要翻译：本发明的一个实施例是一种SRAM存储器阵列，其包括具有每个单元的存储器单元，所述存储器单元包含七个器件，其中存储数据的真实和补码的基本存储节点由六个器件构成，形成交叉耦合触发器，触发器电池。该单元的一个内部存储节点连接到单独的读通设备，该设备将该节点的状态传递到用于单端感测的本地位线（LBL），该单独的读通道设备的门连接到单独的读字线。

10. 发明授权

US07289369B2 DRAM hierarchical data path 有权
标题翻译： DRAM分层数据路径
公开(公告)号：US07289369B2
公开(公告)日：2007-10-30
申请号：US11108369
申请日：2005-04-18
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C7/10
CPC分类号： G11C11/4091 , G11C11/4085 , G11C11/4097
摘要： A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global read bit line (GRBL). When a cell storing a high is selected, the cell drives the LBL high, which turns the sense device on to drive the GRBL low. Segments may be used individually (as a macro) or combined with other segments sharing a common GRBL.
摘要翻译：分层DRAM阵列，DRAM宏和逻辑芯片，其中包含嵌入逻辑的DRAM宏。 DRAM阵列列以与每个段中的局部位线（LBL）连接的小数量（例如，2-64）的单元进行分段。每个LBL驱动驱动全局读取位线（GRBL）的检测器件。当选择存储高电平的单元时，单元驱动LBL为高电平，使开启感测器件以驱动GRBL为低电平。分段可以单独使用（作为宏）或与共享共同GRBL的其他段组合使用。

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