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1. 发明授权

US5942917A High speed ratioed CMOS logic structures for a pulsed input environment 失效
标题翻译：用于脉冲输入环境的高速比CMOS逻辑结构
公开(公告)号：US5942917A
公开(公告)日：1999-08-24
申请号：US999102
申请日：1997-12-29
申请人： Barbara A. Chappell , Terry I. Chappell , Mark S. Milshtein , Thomas D. Fletcher
发明人： Barbara A. Chappell , Terry I. Chappell , Mark S. Milshtein , Thomas D. Fletcher
IPC分类号： H03K19/20 , H03K19/0948 , H03K19/096 , H03K19/094
CPC分类号： H03K19/0963 , H03K19/0948
摘要： A logic structure adapted to receive pulsed active input signals produces a logical output with a very small inherent switching delay. Pull-down transistors and complementary pull-up transistors are ratioed such that the default logical output level remains close to nominal even when the logic structure sinks or sources a DC current. When the pulsed input signals are inactive, no DC current path is enabled.
摘要翻译：适于接收脉冲有源输入信号的逻辑结构产生具有非常小的固有切换延迟的逻辑输出。比较下拉晶体管和互补上拉晶体管，使得默认逻辑输出电平保持接近标称值，即使当逻辑结构吸收或输出直流电流时。当脉冲输入信号无效时，不启用直流电流路径。

2. 发明授权

US5204841A Virtual multi-port RAM 失效
标题翻译：虚拟多端口RAM
公开(公告)号：US5204841A
公开(公告)日：1993-04-20
申请号：US873672
申请日：1992-04-23
申请人： Barbara A. Chappell , Terry I. Chappell , Mahmut K. Ebcioglu , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Mahmut K. Ebcioglu , Stanley E. Schuster
IPC分类号： G06F12/04 , G06F12/08 , G11C7/10 , G11C8/12 , G11C8/16
CPC分类号： G11C8/16 , G06F12/04 , G11C7/103 , G11C8/12 , G06F12/0855
摘要： A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
摘要翻译：虚拟多端口RAM（VMPRAM）结构具有自动端口排序和单端口阵列密度和速度。 VMPRAM采用输入触发的自复位宏，采用流水线架构，在一个机器周期内提供多个自定时片上循环。 VMPRAM集成了一个SRAM，分为许多输入触发，自复位，快速循环模块。定时信号从所选择的SRAM块导出，用于将下一个选择信号和数据释放到SRAM块。 SRAM块输入只是数据输入总线和选择字线和位线对所需的解码信号，SRAM块周期只是为字线和位线提供足够的脉冲宽度所需的时间。每个SRAM块和访问SRAM块的路径中的所有电路块都是输入触发和自复位。多个地址和数据输入锁存器在驱动器处被复用到SRAM段的真实和补码总线，这些总线是自复位的。类似地，所选的SRAM块将数据读出到自复位总线上，并且通过相邻块的释放来将地址和数据输入锁存在用于释放信号的块中，并且这些块都是自复位的。

3. 发明授权

US4525731A Semiconductor conversion of optical-to-electrical energy 失效
标题翻译：光电能的半导体转换
公开(公告)号：US4525731A
公开(公告)日：1985-06-25
申请号：US454784
申请日：1982-12-30
申请人： Terry I. Chappell , Thomas N. Jackson , Jerry M. Woodall
发明人： Terry I. Chappell , Thomas N. Jackson , Jerry M. Woodall
IPC分类号： H01L31/10 , H01L27/144 , H01L31/0352 , H01L31/101 , H01L31/109 , H01L27/14 , H01L29/88 , H01L31/06
CPC分类号： H01L27/1446 , H01L31/0352 , H01L31/101 , H01L31/109
摘要： Optical-to-electrical conversion is accomplished using an undoped region bounded by a tunneling junction of the order of the mean free path of an electron. A number of regions are assembled in series with larger thickness away from the light incident surface. The thickness and doping of the regions for maximum effectiveness in monochromatic light are tailored to produce similar quantities of carriers from the light. A nine section GaAs structure with 50 .ANG. n.sup.+ and p.sup.+ tunneling bounding regions has a 90% quantum efficiency and delivers a 5 volt output with a 0.35 picosecond transit time.
摘要翻译：使用由电子平均自由程的阶数的隧道结界定的未掺杂区域实现光电转换。许多区域与光入射表面相比较大地组合成较大的厚度。针对在单色光中最大效能的区域的厚度和掺杂被定制以从光产生相似量的载流子。具有50个ANGSTROM n +和p +隧道界限区域的九段GaAs结构具有90％的量子效率，并以0.35皮秒的传输时间提供5伏输出。

4. 发明授权

US4295002A Heterojunction V-groove multijunction solar cell 失效
标题翻译：异相结V型多结太阳能电池
公开(公告)号：US4295002A
公开(公告)日：1981-10-13
申请号：US161820
申请日：1980-06-23
申请人： Terry I. Chappell , Jerry M. Woodall
发明人： Terry I. Chappell , Jerry M. Woodall
IPC分类号： H01L31/04 , H01L25/04 , H01L27/142 , H01L31/0352 , H01L31/043 , H01L31/047 , H01L31/0725 , H01L31/0735 , H01L31/074 , H01L31/10 , H01L31/06
CPC分类号： H01L31/0725 , H01L31/035281 , H01L31/043 , H01L31/047 , H01L31/0735 , H01L31/074 , Y02E10/544
摘要： A solar cell is disclosed with V-grooves which are series connected, but electrically isolated, indirect bandgap solar cells which are responsive to different light frequencies on both sides of a semi-insulating optically transparent substrate. The device has a very high conversion efficiency of approximately 40% and high open-circuit voltage and low series resistance. An exemplary structure in accordance with this disclosure has a series of silicon V-groove cells on one side and another series of GaAlAs V-groove cells on the other side. The cells are of generally trapezoidal cross-section. The difference between the characteristics of the Si cell and the GaAlAs cell is matched by control of the number of V-grooves.
摘要翻译：公开了一种太阳能电池，其具有串联连接但电绝缘的间接带隙太阳能电池，其对半绝缘光学透明基板两侧的不同光频有反应。该器件具有大约40％的非常高的转换效率和高开路电压和低串联电阻。根据本公开的示例性结构在一侧具有一系列硅V槽单元，另一侧具有另一系列GaAlAs V沟槽单元。电池通常是梯形的横截面。通过控制V槽的数量来匹配Si电池和GaAlAs电池的特性之间的差异。

5. 发明授权

US5481495A Cells and read-circuits for high-performance register files 失效
标题翻译：用于高性能寄存器文件的单元和读取电路
公开(公告)号：US5481495A
公开(公告)日：1996-01-02
申请号：US226161
申请日：1994-04-11
申请人： Walter H. Henkels , Wei Hwang , Terry I. Chappell
发明人： Walter H. Henkels , Wei Hwang , Terry I. Chappell
IPC分类号： G11C8/16 , G11C7/00
CPC分类号： G11C8/16
摘要： A high-performance register file is implemented in a multi-block structure consisting of sub-arrays and associated multiplexing circuits. For a given port, the outputs of all multiplexer circuits are dotted together to form a single global output. The multiplexer circuits may be completely external to the cells ("standard" approach), or distributed and integrated into the cells ("alternate" approach). The register cells arranged as such, may or may not contain extra latches, pass gates, and controls arranged so that the file may be fully tested via LSSD.
摘要翻译：高性能寄存器文件以由子阵列和相关复用电路组成的多块结构实现。对于给定的端口，所有多路复用器电路的输出被点缀在一起以形成单个全局输出。多路复用器电路可以完全在单元外部（“标准”方法）外部，或分布并集成到单元中（“替代”方式）。这样布置的寄存器单元可以包含或可以不包含额外的锁存器，传递门和布置的控件，使得文件可以经由LSSD被完全测试。

6. 发明授权

US4845677A Pipelined memory chip structure having improved cycle time 失效
标题翻译：流水线存储芯片结构具有改进的周期时间
公开(公告)号：US4845677A
公开(公告)日：1989-07-04
申请号：US86136
申请日：1987-08-17
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： G11C11/41 , G11C7/10 , G11C7/12 , G11C8/12 , G11C11/401 , G11C11/413
CPC分类号： G11C8/12 , G11C7/1039 , G11C7/12
摘要： A semiconductor random access memory chip wherein the cycle time is less than the access time for any combination of read or write sequence. The semiconductor random access memory chip is partitioned into relatively small sub-arrays with local decoding and precharging. The memory chip operates in a pipelined manner with more than one access propagating through the chip at any given time and wherein the cycle time is limited by sub-array cycles wherein the cycle time is less than the access time for a memory chip having cycle times greater than access times for accesses through the same sub-array. The memory chip also incorporates dynamic storage techniques for achieving very fast access and precharge times.

7. 发明授权

US4843261A Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories 失效
标题翻译：半导体存储器的互补输出，高密度CMOS解码器/驱动电路
公开(公告)号：US4843261A
公开(公告)日：1989-06-27
申请号：US161813
申请日：1988-02-29
申请人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Stanley E. Schuster
IPC分类号： G11C11/413 , G11C8/10 , G11C11/408
CPC分类号： G11C8/10
摘要： A high performance decoder/driver circuit for a semiconductor memory having A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .phi.PC line is included for receiving a .phi.PC precharge clock signal thereon and a .phi.R line is provided for receiving a .phi.R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node of the decoder and to AN and AN lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the AN line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line and is further responsive to the second selection signal to provide an output signal on a second memory word line.

8. 发明授权

US4533940A High spatial resolution energy discriminator 失效
标题翻译：高空间分辨率能量鉴别器
公开(公告)号：US4533940A
公开(公告)日：1985-08-06
申请号：US503945
申请日：1983-06-13
申请人： Barbara A. Chappell , Terry I. Chappell , Jerry M. Woodall
发明人： Barbara A. Chappell , Terry I. Chappell , Jerry M. Woodall
IPC分类号： H04N5/30 , H01J29/45 , H01L27/14 , H01L27/146 , H04N9/04
CPC分类号： H01L27/14647 , H01J29/45
摘要： An energy discriminator is provided wherein energy, entering through a receiving surface into a multilayer semiconductor monocrystalline body is converted into hole-electron pair carriers in different particular energy responsive layers and the electrons thereof are collected in potential wells that are asymmetric to electron flow associated with the particular layer.
摘要翻译：提供了一种能量鉴别器，其中通过接收表面进入多层半导体单晶体的能量被转换成不同特定能量响应层中的空穴 - 电子对载流子，并且其电子被收集在与电子流不对称的势阱中特定层。

9. 发明授权

US06204714B1 Variable width pulse generator 有权
标题翻译：可变宽度脉冲发生器
公开(公告)号：US06204714B1
公开(公告)日：2001-03-20
申请号：US09159548
申请日：1998-09-24
申请人： Mark S. Milshtein , Thomas D. Fletcher , Kevin (Xia) Dai , Terry I. Chappell , Milo D. Sprague
发明人： Mark S. Milshtein , Thomas D. Fletcher , Kevin (Xia) Dai , Terry I. Chappell , Milo D. Sprague
IPC分类号： H03K104
CPC分类号： H03K5/133 , H03K5/00006 , H03K5/156 , H03K2005/00058
摘要： A variable width pulse generator. The pulse generator includes a pulse circuit responsive to a reset signal to provide a pulse circuit signal. A variable delay reset loop path, coupled to the pulse circuit, is responsive to the pulse circuit signal to provide the reset signal. A control signal may vary the width of a pulse generated by the circuit by varying the length of a delay associated with the reset loop path. Both a coarse control signal, such as a signal that selectively removes a logic element in the reset loop path, and a fine control signal, such as a signal that controls a tunable delay element in the reset loop path, may be used to adjust the pulse width.
摘要翻译：可变宽度脉冲发生器。脉冲发生器包括响应于复位信号的脉冲电路以提供脉冲电路信号。耦合到脉冲电路的可变延迟复位环路径响应脉冲电路信号以提供复位信号。控制信号可以通过改变与复位环路径相关联的延迟的长度来改变由电路产生的脉冲的宽度。可以使用诸如选择性地去除复位环路径中的逻辑元件的信号和诸如控制复位环路径中的可调谐延迟元件的信号的精细控制信号的粗略控制信号来调整脉冲宽度。

10. 发明授权

US5542067A Virtual multi-port RAM employing multiple accesses during single machine cycle 失效
标题翻译：虚拟多端口RAM在单机周期中采用多次访问
公开(公告)号：US5542067A
公开(公告)日：1996-07-30
申请号：US345328
申请日：1994-11-21
申请人： Barbara A. Chappell , Terry I. Chappell , Mahmut K. Ebcioglu , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Mahmut K. Ebcioglu , Stanley E. Schuster
IPC分类号： G11C7/10 , G11C8/16 , G05F12/00
CPC分类号： G11C8/16 , G11C7/103 , G11C7/1072
摘要： A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
摘要翻译：虚拟多端口RAM（VMPRAM）结构具有自动端口排序和单端口阵列密度和速度。 VMPRAM采用输入触发的自复位宏，采用流水线架构，在一个机器周期内提供多个自定时片上循环。 VMPRAM集成了一个SRAM，分为许多输入触发，自复位，快速循环模块。定时信号从所选择的SRAM块导出，用于将下一个选择信号和数据释放到SRAM块。 SRAM块输入只是数据输入总线和选择字线和位线对所需的解码信号，SRAM块周期只是为字线和位线提供足够的脉冲宽度所需的时间。每个SRAM块和访问SRAM块的路径中的所有电路块都是输入触发和自复位。多个地址和数据输入锁存器在驱动器处被复用到SRAM段的真实和补码总线，这些总线是自复位的。类似地，所选的SRAM块将数据读出到自复位总线上，并且通过相邻块的释放来将地址和数据输入锁存在用于释放信号的块中，并且这些块都是自复位的。

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