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1. 发明公开

EP0436823A1 Signalpegelwandler 失效
标题翻译： Signalpegelwandler。
公开(公告)号：EP0436823A1
公开(公告)日：1991-07-17
申请号：EP90122762.9
申请日：1990-11-28
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Barré, Claude, Dipl.-Ing.
IPC分类号： H03K19/0175 , H03K19/0185
CPC分类号： H03M7/22 , H03K17/6264 , H03K17/693 , H03K19/017527 , H03K19/018514
摘要： Ein Signalpegelwandler zur Umsetzung von C-MOS-Logik-Eingangssignalpegeln auf CML-Eingangssignalpegeln auf CML- bzw. ECL-Ausgangssignalpegel besteht aus einer als Stromschalter dienenden Differenzverstärkeranordnung mit einem ersten und einem zweiten Verstärkerast. Der erste Verstärkerast weist einen Steuertransistor (ST) und der zweite Verstärkerast einen Referenztransistor (RT) auf. Um den Signalpegelwandler zur Bildung von Logik verwenden zu können, ist der Steuertransistor (ST) als Feldeffekttransistor ausgebildet, da Feldeffekttransistoren gegenüber Bipolartransistoren kein Sättigungsverhalten aufweisen.
摘要翻译：用于将CML输入信号电平上的CMOS逻辑输入信号电平转换为CML或ECL输出信号电平的信号电平转换器包括用作具有第一和第二放大器分支的电流开关的差分放大器装置。第一放大器分支具有控制晶体管（ST），第二放大器支路具有参考晶体管（RT）。为了能够使用信号电平转换器来形成逻辑，控制晶体管（ST）被设计为场效应晶体管，因为与双极晶体管不同，场效应晶体管没有饱和响应。

2. 发明申请

WO2003083761A1 VERFAHREN ZUR KODIERUNG EINER SEQUENZ VON DATENBYTES, INSBESONDERE ZUR ÜBERTRAGUNG ÜBER EINE LUFTSCHNITTSTELLE 审中-公开
标题翻译：方法对编码数据的字节序列，尤其是对于传输通过空中接口
公开(公告)号：WO2003083761A1
公开(公告)日：2003-10-09
申请号：PCT/DE2003/000854
申请日：2003-03-17
申请人： SIEMENS AKTIENGESELLSCHAFT , CUYLEN, Michael
发明人： CUYLEN, Michael
IPC分类号： G06K7/00
CPC分类号： G06K7/10039 , G06K7/0008 , H03M7/22
摘要： Das Verfahren betrifft die Kodierung einer Sequenz von Datenbytes (BY1,BY2), wobei jeweils zwei Bit (B1,B2) eines Datenbytes ein Doppelbit (D1-D4) bilden und jedes Doppelbit durch einen Zeitschlitzrahmen (ZR1-ZR4) mit zumindest vier Zeitschlitzen (ZS1-ZS4) repräsentiert werden, welche einen Ein- oder Auswert (Z1,Z0) annehmen können. Die Kodierung erfolgt in einem Zeitschlitzrahmen so, dass zumindest ein Zeitschlitz mit einem Auswert an einer Position (AF) vorbelegt ist, und die nicht vorbelegten Zeitschlitze zur Bildung eines logischen Wertes (00,01,10,11) eines Doppelbits höchstens einen Zeitschlitz mit einem Einwert aufweisen. Das Verfahren kann vorteilhaft bei Identifikationssystemen (IS), bei mobilen Datenspeichern (DT) und bei Schreib-/Lesegeräten (SLG) eingesetzt werden. Hiermit ist der Vorteil verbunden, dass eine höhere Datenrate und/oder ein größerer Übertragungsabstand zwischen Schreib-/Lesegerät und mobilem Datenspeicher erreicht werden kann.
摘要翻译：该方法涉及的数据字节（BY1，BY2）的序列的编码中，在每种情况下两个位（B1，B2）构成数据字节，一个双位（D1-D4），并通过一个时隙帧（ZR1-ZR4），每个双位具有至少四个时隙（ ZS1-ZS4）被表示可开或关的值（Z1，Z0）承担。编码是在一个时隙帧，使得在一个位置（AF）与关断值的至少一个时隙是预定义的，并且没有预分配的时隙，以形成在与最多一个时隙中的双位的逻辑值（00,01,10,11）执行对价值。可以有利地在识别系统（IS），其中所述移动数据存储器（DT）和读/写设备（SLG）的使用的方法。这具有更高的数据速率和/或读/写器和移动数据存储器之间的较大的通信距离，可以实现的优点。

3. 发明申请

WO1991012669A1 CODING CIRCUIT 审中-公开
标题翻译：编码电路
公开(公告)号：WO1991012669A1
公开(公告)日：1991-08-22
申请号：PCT/DE1991000120
申请日：1991-02-15
申请人： SIEMENS AKTIENGESELLSCHAFT , ZOJER, Bernhard
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H03M07/22
CPC分类号： H03M7/22 , H03M1/0809 , H03M1/36
摘要： Coding circuit which forms a ''1 from N code'' from an ''X from N code'', consisting of partial circuits, in which each position of the X from N code forms the input value of a partial circuit, with the special feature that each partial circuit consists of three emitter-coupled transistor pairs (T1, T2; T3, T4; T5, T6), that in addition the emitter terminal of a first transistor (T1) is interconnected with the emitter terminal of a second transistor (T2) and taken via a current course (Ie) to reference potential, that the collector terminal of the first transistor (T1) is interconnected with the emitter terminal of a third transistor (T3) and the emitter terminal of the fourth transistor (T4), that the collector terminal of the second transistor (T2) is interconnected with the emitter terminal of a fifth transistor (T5) and the emitter terminal of a sixth transistor (T6), that the base terminal of the third transistor (T3) of each partial circuit is interconnected via a level shift circuit (PS) with the base terminal of the first transistor (T1), that the base terminal of the fourth transistor (T4) of each partial circuit is connected via a further level shift circuit (PS) to the base terminal of the second transistor (T2) of the same partial circuit, that the collector terminal of the transistor (T3) of each partial circuit together with the collector terminal of the fifth transistor (T5) of said partial circuit forms the signal output (n-2; n-1; n; n+1), that the base terminal of the third transistor (T3) together with the base terminal of the fourth transistor (T4) forms a symmetrical signal input of this partial circuit, that the base terminal of the third transistor (T3) of a partial circuit (Can, Cbn-1, kn, ...) is interconnected with the base terminal of the fifth transistor (T5) of the partial circuit (..., Tan+1, Kn+1, Cbn, ...), which has the next higher position of the X from N code as the input value, that the base terminal of the fourth transistor (T4) of a partial circuit (..., Can, Cbn-1, Kn ...) is interconnected with the base terminal of the sixth transistor (T6) of the partial circuit (..., Can+1, Cbn, Kn+1, ...), the input value of which is the next higher position of the X from N code and that the collector terminal of the fourth transistor (T4) together with the collector terminal of the sixth transistor (T6) of a partial circuit (..., Can, Cbn-1, Kn, ...) is connected to the signal output (..., n-1, ...) of the partial circuit, the input value of which is the next lower position of the X from N code.
摘要翻译：编码电路从“N码”的“X码”形成“1”，由部分电路组成，其中来自N码的X的每个位置形成部分电路的输入值，其中每个部分电路的特征在于三个发射极耦合晶体管对（T1，T2; T3，T4; T5，T6），另外第一晶体管（T1）的发射极端子与第二晶体管晶体管（T2），并通过电流过程（Ie）获取参考电位，第一晶体管（T1）的集电极端子与第三晶体管（T3）的发射极端子和第四晶体管（ T4），第二晶体管（T2）的集电极端子与第五晶体管（T5）的发射极端子和第六晶体管（T6）的发射极端子互连，第三晶体管（T3）的基极端子每个部分电路通过电平转换电路相互连接用第一晶体管（T1）的基极引脚（PS），将每个部分电路的第四晶体管（T4）的基极端经由另一电平移位电路（PS）连接到第二晶体管的基极端子（T2），每个部分电路的晶体管（T3）的集电极端子与所述部分电路的第五晶体管（T5）的集电极端子一起形成信号输出（n-2; N-1; N; n + 1），第三晶体管（T3）的基极端子与第四晶体管（T4）的基极端子形成该部分电路的对称信号输入，第三晶体管（T3）的基极端子部分电路（Can，Cbn-1，kn，...）与部分电路（...，Tan + 1，Kn + 1，Cbn，...）的第五晶体管（T5）的基极端子互连。），其具有来自N代码的X的下一个较高位置作为输入值，部分电路（...，Can，Cbn-1，Kn ...）的第四晶体管（T4）的基极端子）与部分电路（...，Can + 1，Cbn，Kn + 1，...）的第六晶体管（T6）的基极端子互连，其输入值是下一个较高位置 X，并且第四晶体管（T4）的集电极端与部分电路（...，Can，Cbn-1，Kn，...）的第六晶体管（T6）的集电极端子一起是连接到th的信号输出（...，n-1，...） e部分电路，其输入值是来自N代码的X的下一个较低位置。

4. 发明申请

US20040160343A1 EXTENDING NON-VOLATILE MEMORY ENDURANCE USING DATA ENCODING 有权
标题翻译：使用数据编码扩展非易失性存储器的使用寿命
公开(公告)号：US20040160343A1
公开(公告)日：2004-08-19
申请号：US10370413
申请日：2003-02-18
申请人： SUN MICROSYSTEMS, INC.
发明人： Steven T. Sprouse
IPC分类号： H03M007/00
CPC分类号： H03M7/22 , G11C16/3495 , H03K21/403 , H03M7/16
摘要： An embedded system comprising a CPU and non-volatile memory is adapted to extend the endurance of the non-volatile memory through the use of an encoding of information stored in the non-volatile memory. One or more data bits are encoded into a larger number of non-volatile memory bit patterns such that changes to the data bits are distributed across fewer changes per non-volatile memory bit. Non-volatile memory endurance is extended since more changes to the data values are possible than can be supported by underlying changes to individual non-volatile memory bits. Word pre-erase, if present, can be accommodated as well as memory bit failures.
摘要翻译：包括CPU和非易失性存储器的嵌入式系统适于通过使用存储在非易失性存储器中的信息的编码来延长非易失性存储器的耐久性。一个或多个数据位被编码成更大数量的非易失性存储器位模式，使得对数据位的改变分布在每个非易失性存储器位更少的变化。非易失性存储器耐久性被扩展，因为数据值的更多变化可能比单个非易失性存储器位的底层变化可以支持。字预擦除（如果存在）可以适应以及存储器位故障。

5. 发明授权

US4897657A Analog-to-digital converter having error detection and correction 失效
标题翻译：具有错误检测和校正的模数转换器
公开(公告)号：US4897657A
公开(公告)日：1990-01-30
申请号：US205854
申请日：1988-06-13
申请人： James L. Brubaker
发明人： James L. Brubaker
IPC分类号： H03K19/0948 , H03M1/20 , H03M1/36 , H03M7/16 , H03M7/22
CPC分类号： H03M1/206 , H03K19/0948 , H03M7/165 , H03M7/22 , H03M1/365
摘要： Employed is a thermometer-code-to-one-of-n converter having a number of similar portions each of which includes gates each configured to detect a zero-zero-one pattern and to develop a one-of-n signal, gates each configured to detect a one-zero-zero pattern (an invalid pattern) and to develop an error signal, gates configured to combine the error signals, and gates configured to gate the error signals with the one-of-n pattern signals to block (inhibit) one-of-n signals.
摘要翻译：使用的是具有多个相似部分的温度计 - 一对一转换器，每个转换器包括各自被配置为检测零 - 零模式并且开发一个n信号的门，每个门开被配置为检测一零零模式（无效模式）并产生误差信号，被配置为组合所述误差信号的门和被配置为将所述误差信号与所述一对n模式信号进行门控的门禁止）一个n信号。

6. 发明授权

US4712090A Data control circuits 失效
标题翻译：数据控制电路
公开(公告)号：US4712090A
公开(公告)日：1987-12-08
申请号：US672621
申请日：1984-11-19
申请人： Kouichi Yamada
发明人： Kouichi Yamada
IPC分类号： G06F7/00 , G06F5/01 , G06F7/74 , H03M7/14 , H03M7/22 , H03M7/00
CPC分类号： H03M7/22 , G06F5/015 , H03M7/14
摘要： A data control circuit comprises a decoder adapted to generate weighted signals for determining the number of bits of data to be transferred; a detection circuit for detecting the output signals of the decoder to generate weighted signals corresponding to the transfer data bit number; and a propagation circuit responsive to the output signals of the detection circuit thereby to establish a propagation region where a predetermined signal propagates and a non-propagation region where the predetermined signal does not propagate and to generate from the non-propagation region the same number of activation signals as the bits of the data to be transferred.
摘要翻译：数据控制电路包括：解码器，适于产生用于确定要传送的数据的位数的加权信号; 检测电路，用于检测解码器的输出信号以产生对应于传送数据位数的加权信号; 以及响应于检测电路的输出信号的传播电路，从而建立预定信号传播的传播区域和预定信号不传播的非传播区域，并且从非传播区域产生相同数量的激活信号作为要传输的数据的位。

7. 发明授权

US4694278A Integrable decoding circuit 失效
标题翻译：可整合解码电路
公开(公告)号：US4694278A
公开(公告)日：1987-09-15
申请号：US908829
申请日：1986-09-18
申请人： Hans P. Fuchs , Jurgen R. Goetz
发明人： Hans P. Fuchs , Jurgen R. Goetz
IPC分类号： G11C11/408 , G11C11/413 , H03M7/00 , H03M7/22
CPC分类号： H03M7/22 , H03M7/005
摘要： A decoding circuit for decoding information represented by input signals includes: sources of transistors of one channel type in each of four CMOS inverters connected to a first supply potential; sources of transistors of another channel type in each two inverters connected to each other and to one or the other of first connecting points; two first switching transistors of the other channel type each having a drain connected to a first connecting point and a source connected to each other and to a last connecting point; the gates of each of the two first switching transistors being connected to a second input signal or a signal complementary thereto of four further input signals complementary to each other in pairs; a last switching transistor of the other channel type having a drain connected to the last connecting point, a source connected to a second supply potential and a gate connected to an input for an individual input signal; the gates of both transistors of two of the inverters being connected to a first input signal and the gates of both transistors of two of the inverters being connected to an input signal complementary to the first input signal; and further complementary transistors of the one channel type each having a drain connected to one of the connecting points, a source connected to the first supply potential and a gate connected to the gate of the switching transistor connected to the same connecting point.
摘要翻译：用于解码由输入信号表示的信息的解码电路包括：连接到第一电源电位的四个CMOS反相器中的每一个中的一个通道类型的晶体管源; 每个两个逆变器中的另一个通道类型的晶体管的源极彼此连接并连接到第一连接点中的一个或另一个; 另一个通道类型的两个第一开关晶体管的每个具有连接到第一连接点的漏极和彼此连接的源极和最后的连接点; 两个第一开关晶体管中的每一个的栅极连接到彼此互补互补的四个另外的输入信号的第二输入信号或与其互补的信号; 另一通道类型的最后一个开关晶体管具有连接到最后连接点的漏极，连接到第二电源电位的源极和连接到单个输入信号的输入端的栅极; 两个反相器的两个晶体管的栅极连接到第一输入信号，两个反相器的两个晶体管的栅极连接到与第一输入信号互补的输入信号; 以及一个沟道类型的另外的互补晶体管，每个具有连接到一个连接点的漏极，连接到第一电源电位的源极和连接到连接到相同连接点的开关晶体管的栅极的栅极。

8. 发明授权

EP0515424B1 CODIERSCHALTUNG 失效
标题翻译：编码。
公开(公告)号：EP0515424B1
公开(公告)日：1994-05-18
申请号：EP91903388.6
申请日：1991-02-15
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： ZOJER, Bernhard
IPC分类号： H03M7/22 , H03M1/36
CPC分类号： H03M7/22 , H03M1/0809 , H03M1/36
摘要： Coding circuit which forms a ''1 from N code'' from an ''X from N code'', consisting of partial circuits, in which each position of the X from N code forms the input value of a partial circuit, with the special feature that each partial circuit consists of three emitter-coupled transistor pairs (T1, T2; T3, T4; T5, T6), that in addition the emitter terminal of a first transistor (T1) is interconnected with the emitter terminal of a second transistor (T2) and taken via a current course (Ie) to reference potential, that the collector terminal of the first transistor (T1) is interconnected with the emitter terminal of a third transistor (T3) and the emitter terminal of the fourth transistor (T4), that the collector terminal of the second transistor (T2) is interconnected with the emitter terminal of a fifth transistor (T5) and the emitter terminal of a sixth transistor (T6), that the base terminal of the third transistor (T3) of each partial circuit is interconnected via a level shift circuit (PS) with the base terminal of the first transistor (T1), that the base terminal of the fourth transistor (T4) of each partial circuit is connected via a further level shift circuit (PS) to the base terminal of the second transistor (T2) of the same partial circuit, that the collector terminal of the transistor (T3) of each partial circuit together with the collector terminal of the fifth transistor (T5) of said partial circuit forms the signal output (n-2; n-1; n; n+1), that the base terminal of the third transistor (T3) together with the base terminal of the fourth transistor (T4) forms a symmetrical signal input of this partial circuit, that the base terminal of the third transistor (T3) of a partial circuit (Can, Cbn-1, kn, ...) is interconnected with the base terminal of the fifth transistor (T5) of the partial circuit (..., Tan+1, Kn+1, Cbn, ...), which has the next higher position of the X from N code as the input value, that the base terminal of the fourth transistor (T4) of a partial circuit (..., Can, Cbn-1, Kn ...) is interconnected with the base terminal of the sixth transistor (T6) of the partial circuit (..., Can+1, Cbn, Kn+1, ...), the input value of which is the next higher position of the X from N code and that the collector terminal of the fourth transistor (T4) together with the collector terminal of the sixth transistor (T6) of a partial circuit (..., Can, Cbn-1, Kn, ...) is connected to the signal output (..., n-1, ...) of the partial circuit, the input value of which is the next lower position of the X from N code.

9. 发明授权

EP0217104B1 Integrierbare Dekodierschaltung 失效
标题翻译：解码器可实现为集成电路
公开(公告)号：EP0217104B1
公开(公告)日：1990-06-27
申请号：EP86111590.5
申请日：1986-08-21
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Fuchs, Hans Peter, Dipl.-Phys. , Goetz, Jürgen R., Dr. Dipl.-Phys.
IPC分类号： H03M7/22
CPC分类号： H03M7/22 , H03M7/005

10. 发明专利

JPS5974723A Pulse synthesizing circuit 失效
标题翻译：脉冲合成电路
公开(公告)号：JPS5974723A
公开(公告)日：1984-04-27
申请号：JP18364982
申请日：1982-10-21
申请人： Yaskawa Electric Mfg Co Ltd
发明人： HARA KENJI
IPC分类号： H03K5/15 , H03K5/00 , H03K5/156 , H03K21/02 , H03K23/00 , H03M7/22
CPC分类号： H03M7/22
摘要： PURPOSE:To synthesize pulse signals with a simple circuit by converting those pulse signals into binary numbers. CONSTITUTION:The position detection is carried out by an encoder for a servo mechanism of a robbot. A pair of signals having a phase difference are delivered from an encoder. The outputs of two encoders are synthesized to obtain the information on the revolving angle. The output signals A1 and B1 of the 1st encoder and the output signals A2 and B2 of the 2nd encoder are converted into binary signals C, D, E and F respectively. These binary signals are added together by a full adder 12. The binary signal, i.e., a result of addition is converted into a double phase signal to obtain output signals A3 and B3.
摘要翻译：目的：通过将这些脉冲信号转换为二进制数，通过简单的电路合成脉冲信号。构成：位置检测由Robbot伺服机构的编码器进行。具有相位差的一对信号从编码器传送。合成两个编码器的输出，以获得有关旋转角度的信息。第一编码器的输出信号A1和B1以及第二编码器的输出信号A2和B2分别转换成二进制信号C，D，E和F. 这些二进制信号通过全加器12相加在一起。二进制信号，即相加结果被转换成双相信号以获得输出信号A3和B3。

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