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1. 发明授权

US07308593B2 Interlocked synchronous pipeline clock gating 有权
标题翻译：联锁同步管道时钟门控
公开(公告)号：US07308593B2
公开(公告)日：2007-12-11
申请号：US11376544
申请日：2006-03-14
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： H04L5/00 , G06F9/30
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
摘要翻译：一种包括管道的集成电路和操作管道的方法。流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

2. 发明授权

US07065665B2 Interlocked synchronous pipeline clock gating 有权
公开(公告)号：US07065665B2
公开(公告)日：2006-06-20
申请号：US10262769
申请日：2002-10-02
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： H04L5/00 , G06F9/30
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

3. 发明授权

US07685457B2 Interlocked synchronous pipeline clock gating 失效
标题翻译：联锁同步管道时钟门控
公开(公告)号：US07685457B2
公开(公告)日：2010-03-23
申请号：US11846847
申请日：2007-08-29
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
摘要翻译：一种包括管道的集成电路和操作管道的方法。流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

4. 发明授权

US07475227B2 Method of stalling one or more stages in an interlocked synchronous pipeline 有权
标题翻译：在联锁同步管道中停止一个或多个阶段的方法
公开(公告)号：US07475227B2
公开(公告)日：2009-01-06
申请号：US11375989
申请日：2006-03-14
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： G06F9/30 , H04L5/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： A method of operating an integrated circuit including a pipeline and a method of stalling stages in the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
摘要翻译：一种操作包括流水线的集成电路的方法和在管线中停止级的方法。流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

5. 发明授权

US07076681B2 Processor with demand-driven clock throttling power reduction 失效
标题翻译：处理器采用需求驱动的时钟节流功率降低
公开(公告)号：US07076681B2
公开(公告)日：2006-07-11
申请号：US10187698
申请日：2002-07-02
申请人： Pradip Bose , Daniel M. Citron , Peter W. Cook , Philip G. Emma , Hans M. Jacobson , Prabhakar N. Kudva , Stanley E. Schuster , Jude A. Rivers , Victor V. Zyuban
发明人： Pradip Bose , Daniel M. Citron , Peter W. Cook , Philip G. Emma , Hans M. Jacobson , Prabhakar N. Kudva , Stanley E. Schuster , Jude A. Rivers , Victor V. Zyuban
IPC分类号： G06F1/04
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3802 , G06F9/3836 , G06F9/384 , G06F9/3867 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要： A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.
摘要翻译：同步集成电路，如标量处理器或超标量处理器。电路组件或单元由公共系统时钟计时并同步。至少两个时钟单元包括多个寄存器级，例如流水线级。每个时钟单元中的本地时钟发生器将来自一个或多个其他单元的公共系统时钟和失速状态相结合，以调整寄存器时钟频率向上或向下。

6. 发明授权

US06946869B2 Method and structure for short range leakage control in pipelined circuits 失效
标题翻译：流水线电路短程泄漏控制的方法和结构
公开(公告)号：US06946869B2
公开(公告)日：2005-09-20
申请号：US10685863
申请日：2003-10-15
申请人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
发明人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
IPC分类号： H03K5/00 , H03K17/16 , H03K19/00
CPC分类号： H03K19/0016
摘要： Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.
摘要翻译：泄漏电流控制装置包括在序列中执行功能的数据路径中具有一个或多个功能的电路。每个功能具有功率降低逻辑以激励每个相应的功能。泄漏控制电路与功率降低逻辑相互作用，使得功能在控制序列中被激励或断电，使得数据驻留的功能被激励，并且其他功能中的至少一个没有通电。

7. 发明授权

US06608771B2 Low-power circuit structures and methods for content addressable memories and random access memories 失效
标题翻译：用于内容可寻址存储器和随机存取存储器的低功率电路结构和方法
公开(公告)号：US06608771B2
公开(公告)日：2003-08-19
申请号：US09933189
申请日：2001-08-20
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Stanley Everett Schuster , Peter W. Cook
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Stanley Everett Schuster , Peter W. Cook
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method is provided for associating an address with data. The method includes precharging a matchline connected to a plurality of tag match functions to a first potential, wherein each tag match function comprises one or more match logic devices, discharging two tag lines for a first tag bit to ground, and reading a plurality of tag bits and corresponding data bits onto a plurality of tag lines and a plurality of data lines respectively. The method further includes determining a match between the tag bits and data bits, and pulling the matchline to a second potential upon determining a match for each of the tag bits.
摘要翻译：提供了一种用于将地址与数据相关联的方法。该方法包括将连接到多个标签匹配功能的匹配线预先充电到第一电位，其中每个标签匹配功能包括一个或多个匹配逻辑器件，将用于第一标签位的两个标签行放电到地，以及读取多个标签位和相应的数据位分别分配到多个标签行和多条数据线上。该方法还包括确定标签位和数据位之间的匹配，并且在确定每个标签位的匹配时，将匹配线拉到第二电位。

8. 发明授权

US06512397B1 Circuit structures and methods for high-speed low-power select arbitration 失效
标题翻译：用于高速低功耗选择仲裁的电路结构和方法
公开(公告)号：US06512397B1
公开(公告)日：2003-01-28
申请号：US09933188
申请日：2001-08-20
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Peter W. Cook , Stanley Everett Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Peter W. Cook , Stanley Everett Schuster
IPC分类号： H03K1720
CPC分类号： G06F13/14 , Y02D10/14
摘要： A method is provided for selecting a participant to issue. The method includes signaling a domino OR gate arbitration device upon a ready request of a participant having a priority, determining within the domino OR gate arbitration device the relative priority of the participant, signaling the domino OR gate arbitration device through an any-request device upon the ready request of a higher priority participant, and issuing the higher priority participant upon determining the higher priority participant to have a priority highest among participants ready for issue. The method includes gating one of a precharge signal and an evaluate signal of the precharged domino OR gate arbitration device by the ready request of the participant. The method further includes latching a result of the domino OR gate arbitration device and a clock signal, and gating the clock signal by the ready signal of the participant.
摘要翻译：提供了一种用于选择参与者发行的方法。该方法包括在具有优先权的参与者的就绪请求之后发信号通知多米诺骨牌或门仲裁装置，在多米诺诺或门仲裁装置内确定参与者的相对优先级，通过任何请求装置向多米诺骨牌或门仲裁装置发信号确定较高优先权的参与者的准备好的请求，并且在确定较高优先权的参与者之后发出优先权较高的参与者以便在准备发行的参与者中具有最高优先权。该方法包括通过参与者的就绪请求选通预充电多米诺OR门仲裁装置的预充电信号和评估信号之一。该方法还包括锁存多米诺OROR仲裁装置的结果和时钟信号，并通过参与者的就绪信号门控时钟信号。

9. 发明授权

US08949101B2 Hardware execution driven application level derating calculation for soft error rate analysis 有权
标题翻译：软件错误率分析的硬件执行驱动应用级降额计算
公开(公告)号：US08949101B2
公开(公告)日：2015-02-03
申请号：US13271827
申请日：2011-10-12
申请人： Pradip Bose , Meeta S. Gupta , Prabhakar N. Kudva , Daniel A. Prener
发明人： Pradip Bose , Meeta S. Gupta , Prabhakar N. Kudva , Daniel A. Prener
IPC分类号： G01R31/3181 , G06F17/50 , G01R31/3183
CPC分类号： G01R31/31816 , G01R31/318357 , G06F17/5022
摘要： Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information. The machine derating information is combined with the application derating information to generate at least one soft error rate value for the integrated circuit device design.
摘要翻译：提供了用于预测软错误对集成电路器件设计的影响的机制。数据处理系统被配置为实现统一的降额工具，其包括用于生成机器降额信息的机器降额前端引擎和用于生成应用降额信息的应用降级前端引擎用于集成电路器件设计。机器降额前端引擎执行集成电路设备设计的仿真以生成机器降额信息。应用降级前端引擎在架构上与集成电路设备设计类似的现有硬件上执行应用程序工作负载，并在执行应用程序工作负载期间将故障注入到现有硬件中，以生成应用程序降级信息。机器降额信息与应用降级信息组合以产生用于集成电路设备设计的至少一个软错误率值。

10. 发明授权

US08091050B2 Modeling system-level effects of soft errors 有权
标题翻译：建模软错误的系统级影响
公开(公告)号：US08091050B2
公开(公告)日：2012-01-03
申请号：US12243427
申请日：2008-10-01
申请人： Pradip Bose , Prabhakar N. Kudva , Jude A. Rivers , Pia N. Sanda , John-David Wellman
发明人： Pradip Bose , Prabhakar N. Kudva , Jude A. Rivers , Pia N. Sanda , John-David Wellman
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.
摘要翻译：提供了对软错误的系统级别影响进行建模的机制。提供了在IC设计的概念阶段将器件级和组件级软错误率（SER）分析机制与微架构级性能分析工具集成的机制，从而生成SER分析工具。通过将SER分析工具应用于IC设计，可以生成IC设计的第一个SER简档。在IC设计的后期阶段，获得关于IC设计中逻辑和存储元件的SER漏洞的详细信息，并且基于关于SER漏洞的详细信息来改进第一SER简档，从而为IC生成第二SER简档设计。基于第一SER简档或第二SER简档中的一个，在IC设计的一个或多个阶段进行对IC设计的修改。

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