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11. 发明授权

US07375017B2 Method for fabricating semiconductor device having stacked-gate structure 有权
标题翻译：具有层叠栅结构的半导体器件的制造方法
公开(公告)号：US07375017B2
公开(公告)日：2008-05-20
申请号：US11338579
申请日：2006-01-23
申请人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
发明人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
IPC分类号： H01L21/3205
CPC分类号： H01L21/28052 , H01L29/4933
摘要： A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.
摘要翻译：一种半导体制造方法，该半导体器件具有堆叠栅极结构。通过介电层与衬底绝缘的衬底上形成多晶硅层。在多晶硅层上形成金属闪光层，然后在钛层上形成氮化钨层。使用氮气和氢气对氮化钨层进行退火。依次形成覆盖氮化钨层的钨层和覆盖层。

12. 发明申请

US20050020028A1 Method for fabricating trench isolation 有权
标题翻译：沟槽隔离方法
公开(公告)号：US20050020028A1
公开(公告)日：2005-01-27
申请号：US10690859
申请日：2003-10-22
申请人： Chien-Mao Liao , Tzu-En Ho , Chang-Rong Wu , Chih-How Chang , Sheng-Wei Yang , Sheng-Tsung Chen , Chung-Yuan Lee , Wen-Sheng Liao , Chen-Chou Huang
发明人： Chien-Mao Liao , Tzu-En Ho , Chang-Rong Wu , Chih-How Chang , Sheng-Wei Yang , Sheng-Tsung Chen , Chung-Yuan Lee , Wen-Sheng Liao , Chen-Chou Huang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229
摘要： A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.
摘要翻译：一种形成沟槽隔离的方法。提供具有开口的半导体衬底，其上形成有掩模层。在半导体衬底和沟槽上顺应地形成第一绝缘层，并且沟槽被第一绝缘层填充。将第一绝缘层各向异性地蚀刻到半导体衬底的下面。在半导体衬底和沟槽上形成第二绝缘层。将第二绝缘层平坦化以露出掩模层。

13. 发明授权

US06833311B2 Manufacturing method for a shallow trench isolation region with high aspect ratio 有权
公开(公告)号：US06833311B2
公开(公告)日：2004-12-21
申请号：US10426327
申请日：2003-04-30
申请人： Hsin-Jung Ho , Chang Rong Wu , Tzu En Ho
发明人： Hsin-Jung Ho , Chang Rong Wu , Tzu En Ho
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A manufacturing method for a shallow trench isolation region with high aspect ratio. The method comprises the steps of providing a substrate with a trench therein, forming a first insulation layer on the substrate and inside the trench by high density plasma chemical vapor deposition (HDPCVD), removing the majority of the first insulation layer outside the trench by spray type etching, and forming a second insulation layer on the first insulation layer by low pressure CVD to fill the trench. According to the present invention, a void-free shallow trench isolation with high aspect ration can be achieved.

14. 发明授权

US06828239B2 Method of forming a high aspect ratio shallow trench isolation 有权
标题翻译：形成高深宽比浅沟槽隔离的方法
公开(公告)号：US06828239B2
公开(公告)日：2004-12-07
申请号：US10121504
申请日：2002-04-11
申请人： Tzu En-Ho , Chang Rong Wu , Hsin-Jung Ho
发明人： Tzu En-Ho , Chang Rong Wu , Hsin-Jung Ho
IPC分类号： H01L21301
CPC分类号： H01L21/76224
摘要： A method of forming a high aspect ratio shallow trench isolation in a semiconductor substrate. The method includes the steps of forming a hard mask layer with a certain pattern on the semiconductor substrate, etching a portion of the semiconductor substrate not covered by the hard mask layer to form a high aspect ratio shallow trench in the semiconductor substrate; forming an oxide liner on the bottom and sidewall of the high aspect ratio shallow trench; performing a LPCVD to form a first oxide layer to fill the high aspect ratio shallow trench, a void being formed in the first oxide layer; etching a portion of the first oxide layer to a certain depth of the high aspect ratio shallow trench and to expose the void; and performing a HDPCVD to form a second oxide layer to fill the high aspect ratio shallow trench.
摘要翻译：一种在半导体衬底中形成高纵横比浅沟槽隔离的方法。该方法包括以下步骤：在半导体衬底上形成具有一定图案的硬掩模层，蚀刻未被硬掩模层覆盖的半导体衬底的一部分，以在半导体衬底中形成高纵横比的浅沟槽; 在高纵横比浅沟槽的底部和侧壁上形成氧化物衬垫; 执行LPCVD以形成第一氧化物层以填充高纵横比浅沟槽，在第一氧化物层中形成空隙; 将所述第一氧化物层的一部分蚀刻到所述高纵横比浅沟槽的一定深度并暴露所述空隙; 并且执行HDPCVD以形成第二氧化物层以填充高纵横比浅沟槽。

15. 发明授权

US06737334B2 Method of fabricating a shallow trench isolation structure 有权
标题翻译：制造浅沟槽隔离结构的方法
公开(公告)号：US06737334B2
公开(公告)日：2004-05-18
申请号：US10268522
申请日：2002-10-09
申请人： Tzu-En Ho , Chang Rong Wu , Yi-Nan Chen
发明人： Tzu-En Ho , Chang Rong Wu , Yi-Nan Chen
IPC分类号： H01L218242
CPC分类号： H01L21/76224 , H01L21/31111
摘要： A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.
摘要翻译：一种制造用于半导体器件的STI的方法。该方法包括以下步骤。在半导体衬底上形成沟槽，在沟槽的底部和侧壁上形成衬里氧化物，然后在衬里氧化物上形成衬里氮化物。第一氧化物层通过高密度等离子体化学气相沉积沉积在沟槽中。将第一氧化物层喷雾刻蚀至预定深度，其中喷雾蚀刻溶液的配方为HF / H 2 SO 4 = 0.3〜0.4。沉积第二氧化物层以通过高密度等离子体化学气相沉积填充沟槽以形成浅沟槽隔离结构。

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