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1. 发明授权

US06794270B2 Method for shallow trench isolation fabrication and partial oxide layer removal 有权
标题翻译：浅沟槽隔离制造和部分氧化物层去除的方法
公开(公告)号：US06794270B2
公开(公告)日：2004-09-21
申请号：US10394681
申请日：2003-03-21
申请人： Pei-Ing Lee , Chang Rong Wu , Tzu En Ho , Yi-Nan Chen , Hsien Wen Su
发明人： Pei-Ing Lee , Chang Rong Wu , Tzu En Ho , Yi-Nan Chen , Hsien Wen Su
IPC分类号： H01L2176
CPC分类号： H01L21/31055 , H01L21/31133 , H01L21/31144 , H01L21/76224
摘要： A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench by spin-spraying to cover the oxide layer in the trench. An etchant is then sprayed over the surface of the semiconductor substrate to remove the uncovered oxide layer and expose the surface of the semiconductor substrate. The density of the etchant is less than that of the liquid etching shield. A second oxide layer is deposited in the trench to form isolation without voids or seams.
摘要翻译：一种形成完全沉积的浅沟槽隔离的方法。第一氧化物层在半导体衬底的表面上以及纵横比大于3的沟槽上共形地形成。通过旋转喷涂将液体蚀刻屏蔽填充在沟槽中以覆盖沟槽中的氧化物层。然后将蚀刻剂喷射到半导体衬底的表面上以去除未覆盖的氧化物层并暴露半导体衬底的表面。蚀刻剂的密度小于液体蚀刻屏蔽层的密度。第二氧化物层沉积在沟槽中以形成无空隙或接缝的隔离。

2. 发明授权

US06737334B2 Method of fabricating a shallow trench isolation structure 有权
标题翻译：制造浅沟槽隔离结构的方法
公开(公告)号：US06737334B2
公开(公告)日：2004-05-18
申请号：US10268522
申请日：2002-10-09
申请人： Tzu-En Ho , Chang Rong Wu , Yi-Nan Chen
发明人： Tzu-En Ho , Chang Rong Wu , Yi-Nan Chen
IPC分类号： H01L218242
CPC分类号： H01L21/76224 , H01L21/31111
摘要： A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.
摘要翻译：一种制造用于半导体器件的STI的方法。该方法包括以下步骤。在半导体衬底上形成沟槽，在沟槽的底部和侧壁上形成衬里氧化物，然后在衬里氧化物上形成衬里氮化物。第一氧化物层通过高密度等离子体化学气相沉积沉积在沟槽中。将第一氧化物层喷雾刻蚀至预定深度，其中喷雾蚀刻溶液的配方为HF / H 2 SO 4 = 0.3〜0.4。沉积第二氧化物层以通过高密度等离子体化学气相沉积填充沟槽以形成浅沟槽隔离结构。

3. 发明授权

US06858516B2 Manufacturing method of a high aspect ratio shallow trench isolation region 有权
标题翻译：高深宽比浅沟槽隔离区的制造方法
公开(公告)号：US06858516B2
公开(公告)日：2005-02-22
申请号：US10279511
申请日：2002-10-23
申请人： Tzu-En Ho , Chang Rong Wu , Hsin-Jung Ho
发明人： Tzu-En Ho , Chang Rong Wu , Hsin-Jung Ho
IPC分类号： H01L21/762 , H01L21/8242 , H01L21/76
CPC分类号： H01L21/76224
摘要： A manufacturing method of a high aspect ratio shallow trench isolation region. A substrate with a trench therein is provided and placed into a chamber. A first insulation layer is formed on the substrate as well as inside the trench by high density plasma chemical vapor deposition. The majority of the first insulation layer outside the trench is removed by in situ etching using carbon fluoride as an etching gas with high selectivity for SiO2/SiN etching ratio, and a second insulation layer is formed on the first insulation layer by high density plasma chemical vapor deposition, filling the trench. According to the present invention, a high aspect ratio shallow trench isolation region without voids can thus be achieved.
摘要翻译：高宽比浅沟槽隔离区域的制造方法。提供其中具有沟槽的衬底并将其放置在室中。第一绝缘层通过高密度等离子体化学气相沉积形成在衬底上以及沟内。通过使用氟化碳作为蚀刻气体的原位蚀刻除去沟槽外部的第一绝缘层的大部分，对SiO 2 / SiN蚀刻比率具有高选择性，并且通过高密度等离子体化学品在第一绝缘层上形成第二绝缘层气相沉积，填充沟槽。根据本发明，可以实现无空隙的高纵横比浅沟槽隔离区域。

4. 发明授权

US06743728B2 Method for forming shallow trench isolation 有权
标题翻译：形成浅沟槽隔离的方法
公开(公告)号：US06743728B2
公开(公告)日：2004-06-01
申请号：US10322224
申请日：2002-12-17
申请人： Tzu En Ho , Chang Rong Wu , Tung-Wang Huang , Shing-Yih Shih
发明人： Tzu En Ho , Chang Rong Wu , Tung-Wang Huang , Shing-Yih Shih
IPC分类号： H01L21301
CPC分类号： H01L21/76224 , H01L21/02129 , H01L21/02274 , H01L21/31051 , H01L21/31612 , H01L21/31625
摘要： A method for forming shallow trench isolation. A substrate is provided with a mask layer formed thereon. The mask layer is etched to expose a portion of the substrate, and the portion of the substrate is etched to form a trench. A liner layer is formed on the inside wall of the trench. A first dielectric layer and a sacrificial layer are sequentially deposited on the substrate such that the trench is substantially filled, wherein the first dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). Portions of the first dielectric layer and the sacrificial layer are removed from the trench. A second dielectric layer is deposited on the substrate such that the trench is substantially filled, wherein the second dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). A portion of the second dielectric layer is removed from the trench.
摘要翻译：一种形成浅沟槽隔离的方法。衬底上形成有掩模层。蚀刻掩模层以暴露衬底的一部分，并蚀刻衬底的该部分以形成沟槽。衬垫层形成在沟槽的内壁上。第一电介质层和牺牲层顺序地沉积在衬底上，使得沟槽基本上被填充，其中第一介电层通过高密度等离子体化学气相沉积（HDPCVD）形成。第一电介质层和牺牲层的一部分从沟槽中去除。第二电介质层沉积在衬底上，使得沟槽基本上被填充，其中第二电介质层通过高密度等离子体化学气相沉积（HDPCVD）形成。第二电介质层的一部分从沟槽去除。

5. 发明授权

US06833311B2 Manufacturing method for a shallow trench isolation region with high aspect ratio 有权
公开(公告)号：US06833311B2
公开(公告)日：2004-12-21
申请号：US10426327
申请日：2003-04-30
申请人： Hsin-Jung Ho , Chang Rong Wu , Tzu En Ho
发明人： Hsin-Jung Ho , Chang Rong Wu , Tzu En Ho
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A manufacturing method for a shallow trench isolation region with high aspect ratio. The method comprises the steps of providing a substrate with a trench therein, forming a first insulation layer on the substrate and inside the trench by high density plasma chemical vapor deposition (HDPCVD), removing the majority of the first insulation layer outside the trench by spray type etching, and forming a second insulation layer on the first insulation layer by low pressure CVD to fill the trench. According to the present invention, a void-free shallow trench isolation with high aspect ration can be achieved.

6. 发明授权

US06828239B2 Method of forming a high aspect ratio shallow trench isolation 有权
标题翻译：形成高深宽比浅沟槽隔离的方法
公开(公告)号：US06828239B2
公开(公告)日：2004-12-07
申请号：US10121504
申请日：2002-04-11
申请人： Tzu En-Ho , Chang Rong Wu , Hsin-Jung Ho
发明人： Tzu En-Ho , Chang Rong Wu , Hsin-Jung Ho
IPC分类号： H01L21301
CPC分类号： H01L21/76224
摘要： A method of forming a high aspect ratio shallow trench isolation in a semiconductor substrate. The method includes the steps of forming a hard mask layer with a certain pattern on the semiconductor substrate, etching a portion of the semiconductor substrate not covered by the hard mask layer to form a high aspect ratio shallow trench in the semiconductor substrate; forming an oxide liner on the bottom and sidewall of the high aspect ratio shallow trench; performing a LPCVD to form a first oxide layer to fill the high aspect ratio shallow trench, a void being formed in the first oxide layer; etching a portion of the first oxide layer to a certain depth of the high aspect ratio shallow trench and to expose the void; and performing a HDPCVD to form a second oxide layer to fill the high aspect ratio shallow trench.
摘要翻译：一种在半导体衬底中形成高纵横比浅沟槽隔离的方法。该方法包括以下步骤：在半导体衬底上形成具有一定图案的硬掩模层，蚀刻未被硬掩模层覆盖的半导体衬底的一部分，以在半导体衬底中形成高纵横比的浅沟槽; 在高纵横比浅沟槽的底部和侧壁上形成氧化物衬垫; 执行LPCVD以形成第一氧化物层以填充高纵横比浅沟槽，在第一氧化物层中形成空隙; 将所述第一氧化物层的一部分蚀刻到所述高纵横比浅沟槽的一定深度并暴露所述空隙; 并且执行HDPCVD以形成第二氧化物层以填充高纵横比浅沟槽。

7. 发明授权

US06693006B2 Method for increasing area of a trench capacitor 有权
标题翻译：增加沟槽电容器面积的方法
公开(公告)号：US06693006B2
公开(公告)日：2004-02-17
申请号：US10322111
申请日：2002-12-17
申请人： Hsin-Jung Ho , Chang Rong Wu , Yi-Nan Chen , Tung-Wang Huang
发明人： Hsin-Jung Ho , Chang Rong Wu , Yi-Nan Chen , Tung-Wang Huang
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/3086 , H01L29/66181 , H01L29/945
摘要： A method for increasing area of a trench capacitor. First, a first oxide layer and a first nitride layer are sequentially formed on a substrate. An opening is formed through the first oxide layer and the first nitride layer into the substrate. A part of the first oxide layer exposed in the opening is removed to form a first recess, and then a second nitride layer is formed therein. A second oxide layer is formed in the lower portion of the opening. After a third nitride layer is formed in the upper portion of the opening, the second oxide layer is removed. The substrate in the opening is etched using the first nitride layer, the second nitride layer and the third nitride layer as a mask to form a second recess in the lower portion of the opening. The second nitride layer and the third nitride layer are then removed.
摘要翻译：一种增加沟槽电容器面积的方法。首先，在基板上依次形成第一氧化物层和第一氮化物层。通过第一氧化物层和第一氮化物层形成到衬底中的开口。去除暴露在开口中的第一氧化物层的一部分以形成第一凹部，然后在其中形成第二氮化物层。第二氧化物层形成在开口的下部。在开口的上部形成第三氮化物层后，除去第二氧化物层。使用第一氮化物层，第二氮化物层和第三氮化物层作为掩模来蚀刻开口中的衬底，以在开口的下部形成第二凹部。然后去除第二氮化物层和第三氮化物层。

8. 发明授权

US06586324B2 Method of forming interconnects 有权
标题翻译：形成互连的方法
公开(公告)号：US06586324B2
公开(公告)日：2003-07-01
申请号：US10057085
申请日：2002-01-25
申请人： Tse-Yao Huang , Chih-Ching Lin , Yu-Chi Sun , Chang Rong Wu , Shing-Yih Shih
发明人： Tse-Yao Huang , Chih-Ching Lin , Yu-Chi Sun , Chang Rong Wu , Shing-Yih Shih
IPC分类号： H01L214763
CPC分类号： H01L21/76837 , H01L21/76834
摘要： A method of forming interconnects. An oxide masking layer with patterns is formed overlaying the metal layer. The patterns of the masking layer are transferred into the metal layer so as to form an opening. Then, a silicon nitride liner is conformally formed on the masking layer, the metal layer and the first insulating layer. Next, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask to reduce the aspect ratio of the opening followed by removal of the remaining silicon nitride liner. Then, an insulating layer is deposited to fill the opening.
摘要翻译：形成互连的方法。形成具有图案的氧化物掩模层，覆盖金属层。将掩模层的图案转移到金属层中以形成开口。然后，在掩模层，金属层和第一绝缘层上共形地形成氮化硅衬垫。接下来，通过反应离子蚀刻部分去除氮化硅衬垫和掩模层以留下刻面掩模以减小开口的纵横比，随后除去剩余的氮化硅衬垫。然后，沉积绝缘层以填充开口。

9. 发明授权

US06794266B2 Method for forming a trench isolation structure 有权
标题翻译：形成沟槽隔离结构的方法
公开(公告)号：US06794266B2
公开(公告)日：2004-09-21
申请号：US10330660
申请日：2002-12-27
申请人： Shing-Yih Shih , Chien-Mao Liao , Chang Rong Wu
发明人： Shing-Yih Shih , Chien-Mao Liao , Chang Rong Wu
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/76229
摘要： A method for forming a trench isolation structure. First, a substrate having at least one trench is provided. The trench is filled with a spin on glass (SOG) layer. Subsequently, a baking is performed on the SOG layer. The SOG layer is etched back to a predetermined depth. Next, a curing is performed on the remaining SOG layer. Finally, an insulating layer is formed on the remaining SOG layer to fill the trench completely.
摘要翻译：一种形成沟槽隔离结构的方法。首先，提供具有至少一个沟槽的衬底。沟槽充满玻璃（SOG）层上的旋涂。随后，在SOG层上进行烘烤。将SOG层回蚀刻到预定深度。接下来，对剩余的SOG层进行固化。最后，在剩余的SOG层上形成绝缘层以完全填充沟槽。

10. 发明授权

US06770563B2 Process of forming a bottle-shaped trench 有权
标题翻译：形成瓶形沟槽的工艺
公开(公告)号：US06770563B2
公开(公告)日：2004-08-03
申请号：US10336083
申请日：2003-01-03
申请人： Tung-Wang Huang , Chang Rong Wu , Chien-Mao Liao , Hsin-Jung Ho
发明人： Tung-Wang Huang , Chang Rong Wu , Chien-Mao Liao , Hsin-Jung Ho
IPC分类号： H01L21311
CPC分类号： H01L27/1087 , H01L21/3083 , H01L29/66181
摘要： A process of forming a bottle-shaped trench. A semiconductor substrate with a trench is provided, on which a pad layer and hard mask layer are sequentially formed. A dielectric layer is formed on the hard mask layer to fill the trench. Part of the dielectric layer is etched to expose the sidewall of the upper portion of the trench. A spacer is formed on the sidewall. The residual dielectric layer in the trench is removed, and the partial trench not covered by the spacer is etched to a bottle shape.
摘要翻译：形成瓶状沟槽的工艺。提供具有沟槽的半导体衬底，其上依次形成衬垫层和硬掩模层。在硬掩模层上形成电介质层以填充沟槽。蚀刻介电层的一部分以暴露沟槽上部的侧壁。在侧壁上形成间隔物。去除沟槽中的残余介电层，并且不被间隔物覆盖的部分沟槽被蚀刻成瓶形。

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