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1. 发明授权

US06737334B2 Method of fabricating a shallow trench isolation structure 有权
标题翻译：制造浅沟槽隔离结构的方法
公开(公告)号：US06737334B2
公开(公告)日：2004-05-18
申请号：US10268522
申请日：2002-10-09
申请人： Tzu-En Ho , Chang Rong Wu , Yi-Nan Chen
发明人： Tzu-En Ho , Chang Rong Wu , Yi-Nan Chen
IPC分类号： H01L218242
CPC分类号： H01L21/76224 , H01L21/31111
摘要： A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.
摘要翻译：一种制造用于半导体器件的STI的方法。该方法包括以下步骤。在半导体衬底上形成沟槽，在沟槽的底部和侧壁上形成衬里氧化物，然后在衬里氧化物上形成衬里氮化物。第一氧化物层通过高密度等离子体化学气相沉积沉积在沟槽中。将第一氧化物层喷雾刻蚀至预定深度，其中喷雾蚀刻溶液的配方为HF / H 2 SO 4 = 0.3〜0.4。沉积第二氧化物层以通过高密度等离子体化学气相沉积填充沟槽以形成浅沟槽隔离结构。

2. 发明申请

US20050124127A1 Method for manufacturing gate structure for use in semiconductor device 审中-公开
标题翻译：制造用于半导体器件的栅极结构的方法
公开(公告)号：US20050124127A1
公开(公告)日：2005-06-09
申请号：US10726500
申请日：2003-12-04
申请人： Tzu-En Ho , Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu
发明人： Tzu-En Ho , Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L21/4763 , H01L29/49 , H01L29/51
CPC分类号： H01L29/4933 , H01L21/28052 , H01L29/51 , H01L29/517 , H01L29/518
摘要： The present invention provides a method for manufacturing a stacked gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a metal layer, a barrier layer, and a tungsten layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.
摘要翻译：本发明提供一种在半导体器件中制造堆叠栅极结构的方法。该方法包括以下步骤：在半导体衬底上依次形成栅极电介质层，多晶硅层，金属层，势垒层和钨层，在氮气环境中进行快速热退火（RTA）在所述钨层上形成氮化硅层，并将所述多层薄膜结构图案化为规定的形态。

3. 发明授权

US06794270B2 Method for shallow trench isolation fabrication and partial oxide layer removal 有权
标题翻译：浅沟槽隔离制造和部分氧化物层去除的方法
公开(公告)号：US06794270B2
公开(公告)日：2004-09-21
申请号：US10394681
申请日：2003-03-21
申请人： Pei-Ing Lee , Chang Rong Wu , Tzu En Ho , Yi-Nan Chen , Hsien Wen Su
发明人： Pei-Ing Lee , Chang Rong Wu , Tzu En Ho , Yi-Nan Chen , Hsien Wen Su
IPC分类号： H01L2176
CPC分类号： H01L21/31055 , H01L21/31133 , H01L21/31144 , H01L21/76224
摘要： A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench by spin-spraying to cover the oxide layer in the trench. An etchant is then sprayed over the surface of the semiconductor substrate to remove the uncovered oxide layer and expose the surface of the semiconductor substrate. The density of the etchant is less than that of the liquid etching shield. A second oxide layer is deposited in the trench to form isolation without voids or seams.
摘要翻译：一种形成完全沉积的浅沟槽隔离的方法。第一氧化物层在半导体衬底的表面上以及纵横比大于3的沟槽上共形地形成。通过旋转喷涂将液体蚀刻屏蔽填充在沟槽中以覆盖沟槽中的氧化物层。然后将蚀刻剂喷射到半导体衬底的表面上以去除未覆盖的氧化物层并暴露半导体衬底的表面。蚀刻剂的密度小于液体蚀刻屏蔽层的密度。第二氧化物层沉积在沟槽中以形成无空隙或接缝的隔离。

4. 发明授权

US06960530B2 Method of reducing the aspect ratio of a trench 有权
标题翻译：降低沟槽纵横比的方法
公开(公告)号：US06960530B2
公开(公告)日：2005-11-01
申请号：US10724435
申请日：2003-11-28
申请人： Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu , Hung-Chang Liao
发明人： Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu , Hung-Chang Liao
IPC分类号： H01L21/311 , H01L21/316 , H01L21/762 , H01L21/302
CPC分类号： H01L21/76224 , H01L21/31116 , H01L21/31612
摘要： A method of reducing trench aspect ratio. A trench is formed in a substrate. A conformal Si-rich oxide layer is formed on the surface of the trench by HDPCVD. A conformal first oxide layer is formed on the Si-rich oxide layer by HDPCVD. A conformal second oxide layer is formed on the first oxide layer by LPCVD. Part of the Si-rich oxide layer, the second oxide layer and the first oxide layer are removed by anisotropic etching to form an oxide spacer composed of a remaining Si-rich oxide layer, a remaining second oxide layer and a remaining first oxide layer. The remaining second oxide layer, part of the remaining first oxide layer and part of the Si-rich oxide layer are removed by BOE. Thus, parts of the remaining first and Si-rich oxide layers are formed on the lower surface of the trench, thereby reducing the trench aspect ratio.
摘要翻译：减小沟槽纵横比的方法。在衬底中形成沟槽。通过HDPCVD在沟槽的表面上形成共形的富Si氧化物层。通过HDPCVD在富Si氧化物层上形成保形第一氧化物层。通过LPCVD在第一氧化物层上形成保形的第二氧化物层。通过各向异性蚀刻去除部分富Si氧化物层，第二氧化物层和第一氧化物层，以形成由剩余的富Si氧化物层，剩余的第二氧化物层和剩余的第一氧化物层组成的氧化物间隔物。剩余的第二氧化物层，剩余的第一氧化物层的一部分和富Si氧化物层的一部分被BOE除去。因此，剩余的第一和富Si氧化物层的一部分形成在沟槽的下表面上，从而减小沟槽纵横比。

5. 发明授权

US06900118B2 Method for preventing contact defects in interlayer dielectric layer 有权
标题翻译：防止层间电介质层接触缺陷的方法
公开(公告)号：US06900118B2
公开(公告)日：2005-05-31
申请号：US10727966
申请日：2003-12-04
申请人： Kaan-Lu Tzou , Yan-Hong Chen , Yi-Nan Chen , Chang-Rong Wu
发明人： Kaan-Lu Tzou , Yan-Hong Chen , Yi-Nan Chen , Chang-Rong Wu
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/02129 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/31612 , H01L21/31625 , H01L21/76802 , H01L21/76819 , H01L21/76826 , H01L21/76829
摘要： A method of forming an interlayer dielectric (ILD) layer. A dielectric layer containing boron and phosphorous is formed overlying a substrate. A plasma treatment is subsequently performed on the dielectric layer using argon or nitrogen as a process gas. A capping layer is formed in-situ overlying the dielectric layer to serve as the ILD layer with the dielectric layer. A reflow process is subsequently performed on the ILD layer. A method for preventing formation of etching defects in a contact is also disclosed.
摘要翻译：一种形成层间电介质（ILD）层的方法。在衬底上形成含有硼和磷的电介质层。随后使用氩或氮作为工艺气体在电介质层上进行等离子体处理。在介质层上原位形成覆盖层，作为具有电介质层的ILD层。随后在ILD层上进行回流处理。还公开了防止接触中的蚀刻缺陷形成的方法。

6. 发明授权

US06861333B2 Method of reducing trench aspect ratio 有权
标题翻译：减小沟槽纵横比的方法
公开(公告)号：US06861333B2
公开(公告)日：2005-03-01
申请号：US10727730
申请日：2003-12-04
申请人： Chang-Rong Wu , Seng-Hsiung Wu , Yi-Nan Chen
发明人： Chang-Rong Wu , Seng-Hsiung Wu , Yi-Nan Chen
IPC分类号： H01L21/311 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/762 , H01L21/76
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/02362 , H01L21/31116 , H01L21/3144 , H01L21/31612 , H01L21/3185 , H01L21/76224
摘要： A method of reducing trench aspect ratio. A trench is formed in a substrate. Using HDP-CVD, a conformal first oxide layer is formed on a surface of the trench. A conformal first nitride layer is formed on the first oxide layer. Part of the first nitride layer is removed to cause the first nitride layer to be lower than a top surface of the substrate. Using a BOE solution, the first nitride layer and part of the first oxide layer are removed to leave a remaining first oxide layer on the lower portion of the surface of the trench. Thus, the trench aspect ratio is reduced.
摘要翻译：减小沟槽纵横比的方法。在衬底中形成沟槽。使用HDP-CVD，在沟槽的表面上形成共形的第一氧化物层。在第一氧化物层上形成共形的第一氮化物层。去除部分第一氮化物层以使第一氮化物层低于衬底的顶表面。使用BOE溶液，去除第一氮化物层和第一氧化物层的一部分以在沟槽的表面的下部留下剩余的第一氧化物层。因此，沟槽纵横比减小。

7. 发明申请

US20050048763A1 Method for preventing contact defects in interlayer dielectric layer 有权
公开(公告)号：US20050048763A1
公开(公告)日：2005-03-03
申请号：US10727966
申请日：2003-12-04
申请人： Kaan-Lu Tzou , Yan-Hong Chen , Yi-Nan Chen , Chang-Rong Wu
发明人： Kaan-Lu Tzou , Yan-Hong Chen , Yi-Nan Chen , Chang-Rong Wu
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02129 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/31612 , H01L21/31625 , H01L21/76802 , H01L21/76819 , H01L21/76826 , H01L21/76829
摘要： A method of forming an interlayer dielectric (ILD) layer. A dielectric layer containing boron and phosphorous is formed overlying a substrate. A plasma treatment is subsequently performed on the dielectric layer using argon or nitrogen as a process gas. A capping layer is formed in-situ overlying the dielectric layer to serve as the ILD layer with the dielectric layer. A reflow process is subsequently performed on the ILD layer. A method for preventing formation of etching defects in a contact is also disclosed.

8. 发明授权

US06825094B2 Method for increasing capacitance of deep trench capacitors 有权
标题翻译：增加深沟槽电容器电容的方法
公开(公告)号：US06825094B2
公开(公告)日：2004-11-30
申请号：US10628895
申请日：2003-07-28
申请人： Chang-Rong Wu , Yi-Nan Chen
发明人： Chang-Rong Wu , Yi-Nan Chen
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L27/10864 , H01L27/10867
摘要： A method for increasing the capacitance of deep trench capacitors. The method includes providing a substrate, forming a pad structure on the substrate, forming a photoresist defining the region of the deep trench on the pad structure, forming a deep trench in the substrate, removing the photoresist, forming a capacitor in the lower portion of the deep trench, forming a first insulation layer on the capacitor, forming an epitaxy layer on the sidewall of the deep trench above the first insulation layer as a liner to narrow the dimension of the deep trench, and removing the first insulation layer uncovered by the epitaxy layer.
摘要翻译：一种增加深沟槽电容器电容的方法。该方法包括提供衬底，在衬底上形成衬垫结构，形成限定衬垫结构上的深沟槽区域的光致抗蚀剂，在衬底中形成深沟槽，去除光致抗蚀剂，在下部形成电容器所述深沟槽在所述电容器上形成第一绝缘层，在所述第一绝缘层上方的所述深沟槽的侧壁上形成外延层作为衬垫，以使所述深沟槽的尺寸变窄，以及去除由所述第一绝缘层未覆盖的所述第一绝缘层外延层。

9. 发明申请

US20050001286A1 Memory device with vertical transistors and deep trench capacitors and manufacturing method thereof 审中-公开
标题翻译：具有垂直晶体管和深沟槽电容器的存储器件及其制造方法
公开(公告)号：US20050001286A1
公开(公告)日：2005-01-06
申请号：US10738472
申请日：2003-12-17
申请人： Chang-Rong Wu , Yi-Nan Chen , Tieh-Chiang Wu
发明人： Chang-Rong Wu , Yi-Nan Chen , Tieh-Chiang Wu
IPC分类号： H01L21/8239 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A memory device with vertical transistors and deep trench capacitors. This device includes a substrate containing at least one deep trench and a trench capacitor disposed in the bottom of the deep trench. A conducting wire is disposed on the trench capacitor. A trench top insulating layer, containing a first insulating layer and a second insulating layer surrounded by the first insulating layer, is disposed on the conducting wire. A control gate is disposed on the trench top insulating layer. A buried strap is provided in the substrate beside the conducting wire. A doping area is provided in the substrate beside the control gate. A manufacturing method for forming such memory device is also disclosed.
摘要翻译：具有垂直晶体管和深沟槽电容器的存储器件。该器件包括：衬底，其包含设置在深沟槽底部的至少一个深沟槽和沟槽电容器。导电线设置在沟槽电容器上。包含第一绝缘层和由第一绝缘层围绕的第二绝缘层的沟槽顶部绝缘层设置在导线上。控制栅极设置在沟槽顶部绝缘层上。在导线旁边的衬底中设置有掩埋带。在控制栅极旁边的衬底中提供掺杂区域。还公开了一种用于形成这种存储器件的制造方法。

10. 发明授权

US06693006B2 Method for increasing area of a trench capacitor 有权
标题翻译：增加沟槽电容器面积的方法
公开(公告)号：US06693006B2
公开(公告)日：2004-02-17
申请号：US10322111
申请日：2002-12-17
申请人： Hsin-Jung Ho , Chang Rong Wu , Yi-Nan Chen , Tung-Wang Huang
发明人： Hsin-Jung Ho , Chang Rong Wu , Yi-Nan Chen , Tung-Wang Huang
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/3086 , H01L29/66181 , H01L29/945
摘要： A method for increasing area of a trench capacitor. First, a first oxide layer and a first nitride layer are sequentially formed on a substrate. An opening is formed through the first oxide layer and the first nitride layer into the substrate. A part of the first oxide layer exposed in the opening is removed to form a first recess, and then a second nitride layer is formed therein. A second oxide layer is formed in the lower portion of the opening. After a third nitride layer is formed in the upper portion of the opening, the second oxide layer is removed. The substrate in the opening is etched using the first nitride layer, the second nitride layer and the third nitride layer as a mask to form a second recess in the lower portion of the opening. The second nitride layer and the third nitride layer are then removed.
摘要翻译：一种增加沟槽电容器面积的方法。首先，在基板上依次形成第一氧化物层和第一氮化物层。通过第一氧化物层和第一氮化物层形成到衬底中的开口。去除暴露在开口中的第一氧化物层的一部分以形成第一凹部，然后在其中形成第二氮化物层。第二氧化物层形成在开口的下部。在开口的上部形成第三氮化物层后，除去第二氧化物层。使用第一氮化物层，第二氮化物层和第三氮化物层作为掩模来蚀刻开口中的衬底，以在开口的下部形成第二凹部。然后去除第二氮化物层和第三氮化物层。

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