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    • 1. 发明授权
    • Method for isolation layer for a vertical DRAM
    • 垂直DRAM隔离层方法
    • US07074700B2
    • 2006-07-11
    • US10943699
    • 2004-09-17
    • Cheng-Chih HuangSheng-Wei YangChen-Chou HuangSheng-Tsung Chen
    • Cheng-Chih HuangSheng-Wei YangChen-Chou HuangSheng-Tsung Chen
    • H01L21/22
    • H01L27/10864H01L27/10867H01L27/10876
    • A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.
    • 一种用于在垂直DRAM中形成隔离层的方法。 提供了具有多个第一沟槽的半导体衬底,其中,在每个的侧壁上形成一个环形电介质层,并且各自填充有第一导电层。 在半导体衬底上形成图案化掩模层,并使用图案化掩模层作为蚀刻掩模蚀刻半导体衬底,以形成多个第二沟槽。 去除图案化的掩模层。 每个第二沟槽填充有用作隔离层的绝缘层。 每个第一导电层被蚀刻以形成多个凹槽。 在每个沟槽旁边的半导体衬底中形成用作掩埋带的掺杂区域。 沟槽顶部绝缘层形成在每个沟槽的底表面中。 每个第一沟槽填充有用作栅极的第二导电层。
    • 4. 发明申请
    • Method for isolation layer for a vertical DRAM
    • 垂直DRAM隔离层方法
    • US20050064643A1
    • 2005-03-24
    • US10943699
    • 2004-09-17
    • Cheng-Chih HuangSheng-Wei YangChen-Chou HuangSheng-Tsung Chen
    • Cheng-Chih HuangSheng-Wei YangChen-Chou HuangSheng-Tsung Chen
    • H01L21/8238H01L21/8242
    • H01L27/10864H01L27/10867H01L27/10876
    • A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.
    • 一种用于在垂直DRAM中形成隔离层的方法。 提供了具有多个第一沟槽的半导体衬底,其中,在每个的侧壁上形成一个环形电介质层,并且各自填充有第一导电层。 在半导体衬底上形成图案化掩模层,并使用图案化掩模层作为蚀刻掩模蚀刻半导体衬底,以形成多个第二沟槽。 去除图案化的掩模层。 每个第二沟槽填充有用作隔离层的绝缘层。 每个第一导电层被蚀刻以形成多个凹槽。 在每个沟槽旁边的半导体衬底中形成用作掩埋带的掺杂区域。 沟槽顶部绝缘层形成在每个沟槽的底表面中。 每个第一沟槽填充有用作栅极的第二导电层。