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11. 发明申请

US20120069631A1 MEMORY ELEMENT AND MEMORY DEVICE 有权
标题翻译：存储元件和存储器件
公开(公告)号：US20120069631A1
公开(公告)日：2012-03-22
申请号：US13303544
申请日：2011-11-23
申请人： Shuichiro Yasuda , Tomohito Tsushima , Satoshi Sasaki , Katsuhisa Aratani
发明人： Shuichiro Yasuda , Tomohito Tsushima , Satoshi Sasaki , Katsuhisa Aratani
IPC分类号： G11C11/00
CPC分类号： G11C13/02 , G11C2213/11 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/1625
摘要： A memory device of a resistance variation type, in which data retaining characteristic at the time of writing is improved, is provided. The memory device includes: a plurality of memory elements in which a memory layer is provided between a first electrode and a second electrode so that data is written or erased in accordance with a variation in electrical characteristics of the memory layer; and pulse applying means applying a voltage pulse or a current pulse selectively to the plurality of memory elements. The memory layer includes an ion source layer including an ionic-conduction material and at least one kind of metallic element, and the ion source layer further contains oxygen.
摘要翻译：提供了一种电阻变化型存储器件，其中写入时的数据保持特性得到改善。存储器件包括：多个存储元件，其中存储层设置在第一电极和第二电极之间，使得根据存储层的电特性的变化来写入或擦除数据; 以及对多个存储元件选择性地施加电压脉冲或电流脉冲的脉冲施加装置。存储层包括离子源层，其包括离子传导材料和至少一种金属元素，离子源层还含有氧。

12. 发明申请

US20100259968A1 STORAGE DEVICE AND INFORMATION RERECORDING METHOD 有权
标题翻译：存储设备和信息验证方法
公开(公告)号：US20100259968A1
公开(公告)日：2010-10-14
申请号：US12747413
申请日：2008-12-11
申请人： Tomohito Tsushima , Tsunenori Shiimoto , Shuichiro Yasuda
发明人： Tomohito Tsushima , Tsunenori Shiimoto , Shuichiro Yasuda
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/56 , G11C2213/79
摘要： A storage device that improves ability of adjusting a resistance value level in recording and enables stable verification control is provided. VWL supplied from a second power source to a control terminal of a transistor is increased (increase portion: ΔVWL) for every rerecording by verification control by a WL adjustment circuit. In the case where a variable resistive element is able to record multiple values, ΔVWL is a value variable for every resistance value level of multiple value information. That is, ΔVWL is a value variable according to magnitude relation of a variation range of recording resistance of the variable resistive element due to a current. In the region where the variation range of the recording resistance is large (source-gate voltage VGS of the transistor is small), ΔVWL is small, while in the region where the variation range of the recording resistance is small (VGS is large), ΔVWL is large.
摘要翻译：提供一种存储装置，其提高了在记录中调整电阻值电平的能力并且实现了稳定的验证控制。通过WL调整电路的验证控制，每次重新录制时，从第二电源向晶体管的控制端子提供的VWL增加（增加部分：＆Dgr; VWL）。在可变电阻元件能够记录多个值的情况下，＆Dgr; VWL是多值信息的每个电阻值电平的值变量。也就是说，＆Dgr; VWL是根据由于电流引起的可变电阻元件的记录电阻的变化范围的大小关系的值变量。在记录电阻的变化范围大（晶体管的源极栅极电压VGS小）的区域中，＆Dgr; VWL小，而在记录电阻的变化范围小（VGS大的区域）），＆Dgr; VWL很大。

13. 发明申请

US20100254178A1 STORAGE DEVICE AND INFORMATION RE-RECORDING METHOD 有权
标题翻译：存储设备和信息再记录方法
公开(公告)号：US20100254178A1
公开(公告)日：2010-10-07
申请号：US12745952
申请日：2008-12-11
申请人： Tomohito Tsushima , Tsunenori Shiimoto , Shuichiro Yasuda
发明人： Tomohito Tsushima , Tsunenori Shiimoto , Shuichiro Yasuda
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/56 , G11C13/0011 , G11C13/0069 , G11C2013/0071 , G11C2013/0092 , G11C2213/11 , G11C2213/56 , G11C2213/79
摘要： A storage device capable of reducing a number of cycles necessary for a verify at a time of multi-value recording is provided. An initial value of a potential difference VCG between a gate and a source of a switching transistor at the time of the verify is set to a value varied in accordance with a resistance value level of multi-value information. In the case where a writing side performs a 3-value recording, when “01” is the information, an initial value VGS01 is set to be smaller than VGS=1.7 V corresponding to the target resistance value level “01”, and when “00” is the information, a value is set to be lower than VGS=2.2 V corresponding to the target resistance value level “00” and higher than the above-described VGS01. This can reduce the number of cycles necessary for the verify process.
摘要翻译：提供能够减少多值记录时的验证所需的循环次数的存储装置。在验证时，开关晶体管的栅极和源极之间的电位差VCG的初始值被设定为根据多值信息的电阻值电平而变化的值。在写入方执行3值记录的情况下，当“01”是信息时，初始值VGS01被设定为小于对应于目标电阻值电平“01”的VGS = 1.7V，当“ 00“是相对于目标电阻值电平”00“，高于上述VGS01的VGS = 2.2V的值。这可以减少验证过程所需的周期数。

14. 发明授权

US07786459B2 Memory element and memory device comprising memory layer positioned between first and second electrodes 有权
标题翻译：存储元件和存储器件包括位于第一和第二电极之间的存储器层
公开(公告)号：US07786459B2
公开(公告)日：2010-08-31
申请号：US11280561
申请日：2005-11-15
申请人： Katsuhisa Aratani , Tomohito Tsushima , Akira Kouchiyama , Tetsuya Mizuguchi
发明人： Katsuhisa Aratani , Tomohito Tsushima , Akira Kouchiyama , Tetsuya Mizuguchi
IPC分类号： H01L29/02
CPC分类号： G11C13/0011 , G11C2213/11 , G11C2213/15 , G11C2213/34 , G11C2213/56 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146
摘要： A memory element 10 includes a memory layer 4 positioned between a first electrode 2 and a second electrode 6, in which an element selected from Cu, Ag, and Zn is contained in the memory layer 4 or in a layer 3 in contact with the memory layer 4, a resistance of the memory element 10 is changed by a voltage applied to the memory element 10 to perform recording of information, and in an erasing process of changing from a recorded state of low resistance value of the memory element 10 to an erased state of high resistance value of the memory element 10, a fluctuation, which is caused by an increase of the voltage applied to the memory element 10, of the resistance value of the memory element 10 at the end of the erasing process is within ten times at a maximum.
摘要翻译：存储元件10包括位于第一电极2和第二电极6之间的存储层4，其中选自Cu，Ag和Zn的元素包含在存储层4中或与存储器接触的层3中层4，存储元件10的电阻被施加到存储元件10的电压改变以进行信息的记录，并且在从存储元件10的低电阻值的记录状态改变为擦除的擦除处理存储元件10的高电阻值的状态，由擦除处理结束时的存储元件10的电阻值的升高引起的由存储元件10施加的电压引起的波动为十倍以内最大。

15. 发明授权

US07583525B2 Method of driving storage device 有权
标题翻译：驱动存储装置的方法
公开(公告)号：US07583525B2
公开(公告)日：2009-09-01
申请号：US11738933
申请日：2007-04-23
申请人： Tsunenori Shiimoto , Nobumichi Okazaki , Hironobu Mori , Tomohito Tsushima
发明人： Tsunenori Shiimoto , Nobumichi Okazaki , Hironobu Mori , Tomohito Tsushima
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2013/0092 , G11C2213/11 , G11C2213/51
摘要： A method of driving a storage device including a variable resistance element in which resistance value is changed reversibly between a high resistance state and a low resistance state by applying voltages with different polarities between two electrodes is provided. The storage device includes a plurality of memory cells formed of the variable resistance elements. The method includes the step of applying voltages more than once in combination to the memory cell when the variable resistance element is changed from the low resistance state to the high resistance state.
摘要翻译：提供了一种通过在两个电极之间施加不同极性的电压来驱动包括可变电阻元件的存储装置的方法，其中电阻值在高电阻状态和低电阻状态之间可逆地改变。存储装置包括由可变电阻元件形成的多个存储单元。该方法包括当可变电阻元件从低电阻状态改变为高电阻状态时，将多次电压组合施加到存储单元的步骤。

16. 发明授权

US07560724B2 Storage device with reversible resistance change elements 有权
标题翻译：具有可逆电阻变化元件的存储装置
公开(公告)号：US07560724B2
公开(公告)日：2009-07-14
申请号：US11632594
申请日：2005-07-08
申请人： Katsuhisa Aratani , Tomohito Tsushima , Hiroaki Narisawa , Wataru Otsuka , Hidenari Hachino
发明人： Katsuhisa Aratani , Tomohito Tsushima , Hiroaki Narisawa , Wataru Otsuka , Hidenari Hachino
IPC分类号： H01L45/00 , G11C11/00
CPC分类号： G11C13/0011 , G11C13/0069 , G11C2013/009 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/1675
摘要： It is intended to provide a storage element having an arrangement which becomes able to be manufactured easily with high density. A storage element includes resistance changing elements 10 having recording layers 2, 3 provided between two electrodes 1, 4 and in which resistance values of the recording layers 2, 3 are reversibly changed with application of electric potential with different polarities to these two electrodes 1, 4, at least part of the layers 2, 3 constructing the recording layers of the resistance changing elements 10 being formed commonly by the same layer in a plurality of adjacent memory cells.
摘要翻译：旨在提供具有能够以高密度容易地制造的布置的存储元件。存储元件包括电阻变化元件10，其具有设置在两个电极1,4之间的记录层2,3，并且其中记录层2,3的电阻值可通过向这两个电极1施加不同极性的电位而可逆地改变，如图4所示，构成电阻变化元件10的记录层的层2,3的至少一部分由多个相邻存储单元中的相同层共同形成。

17. 发明授权

US07433220B2 Two variable resistance elements being formed into a laminated layer with a common electrode and method of driving the same 有权
标题翻译：两个可变电阻元件形成为具有公共电极的层压层及其驱动方法
公开(公告)号：US07433220B2
公开(公告)日：2008-10-07
申请号：US11264939
申请日：2005-11-02
申请人： Tsunenori Shiimoto , Katsuhisa Aratani , Masaaki Hara , Tomohito Tsushima
发明人： Tsunenori Shiimoto , Katsuhisa Aratani , Masaaki Hara , Tomohito Tsushima
IPC分类号： G11C11/22
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/32
摘要： A memory element having a configuration in which contents of recorded data can be judged easily and power consumption can be reduced, and a method of driving the same are provided. A memory element 10 of the present invention includes variable resistance elements 11 and 12 whose resistance state changes reversibly between a high resistance state and a low resistance state by applying a voltage of a different polarity between an electrode 1 of one side and an electrode 2 of the other side; the electrode 1 of one side in each element of the two variable resistance elements 11 and 12 is made a common electrode; and the electrode 2 of the other side in each element of the two variable resistance elements 11 and 12 is made independent and is provided respectively with the terminal X and terminal Y, to form a memory cell having two terminals in total.
摘要翻译：具有可以容易地判断记录数据的内容并且能够降低功耗的配置的存储元件及其驱动方法。本发明的存储元件10包括可变电阻元件11和12，其电阻状态在高电阻状态和低电阻状态之间可逆地改变，通过在一侧的电极1和电极2之间施加不同极性的电压另一边; 将两个可变电阻元件11和12的每个元件中的一侧的电极1制成公共电极; 并且两个可变电阻元件11和12的每个元件中的另一侧的电极2被制成独立的并且分别设置有端子X和端子Y，以形成总共具有两个端子的存储单元。

18. 发明授权

US07145791B2 Memory device having variable resistive memory element 有权
标题翻译：具有可变电阻存储元件的存储器件
公开(公告)号：US07145791B2
公开(公告)日：2006-12-05
申请号：US11042959
申请日：2005-01-25
申请人： Tomohito Tsushima , Katsuhisa Aratani , Akira Kouchiyama
发明人： Tomohito Tsushima , Katsuhisa Aratani , Akira Kouchiyama
IPC分类号： G11C11/00
CPC分类号： G11C13/0009 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/11 , G11C2213/15 , G11C2213/34 , G11C2213/79 , H01L27/2436 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A memory device is obtained in which stable recording of information can be performed and a period of time required for the recording of information can be shortened. The memory device includes a memory cell C formed of a memory element Amn having a characteristic in which a resistance value changes when applying between both ends of the memory element Amn a voltage equal to or more than a threshold voltage and a circuit element Tmn as a load connected in series to the memory element Amn; and when an operation to change the memory element Amn from a state of high resistance value to a state of low resistance value is defined as writing and when a voltage applied between both ends of the memory element Amn and the circuit element Tmn is equal to or more than a certain voltage value which is larger than the threshold voltage, the memory device has a characteristic in which a combined resistance value of the memory element Amn and the circuit element Tmn in the memory cell C after writing becomes almost constant value irrespective of the magnitude of applied voltage.
摘要翻译：获得可以执行信息的稳定记录并且可以缩短记录信息所需的时间段的存储器件。存储器件包括由存储元件Amn形成的存储单元C，该存储单元Amn具有当存储元件Amn的两端施加等于或大于阈值电压的电压和电路元件Tmn之间电阻值变化的特性时负载串联连接到存储元件Amn; 并且当将存储元件Amn从高电阻值状态改变为低电阻值的状态的操作被定义为写入时，并且当存储元件Amn和电路元件Tmn的两端之间施加的电压等于或等于大于阈值电压的一定电压值，存储器件具有这样的特性，其中存储元件Amn和写入后存储单元C中的电路元件Tmn的组合电阻值几乎是恒定值，而与施加电压的大小。

19. 发明申请

US20060092685A1 Storage apparatus 有权
标题翻译：储存装置
公开(公告)号：US20060092685A1
公开(公告)日：2006-05-04
申请号：US11245325
申请日：2005-10-05
申请人： Wataru Ootsuka , Tomohito Tsushima , Hidenari Hachino
发明人： Wataru Ootsuka , Tomohito Tsushima , Hidenari Hachino
IPC分类号： G11C11/22
CPC分类号： G11C11/16
摘要： The present invention provides a storage apparatus including a variable resistance element having a recording layer between two electrodes. In the variable resistance element, a resistance value of the recording layer is reversibly changed to one of a value in a high-resistance state and a value in a low-resistance state by applying potentials of different polarities to the two electrodes. An absolute value of a threshold value of an applied signal at a time of change from the high-resistance state to the low-resistance state and an absolute value of a threshold value of an applied signal at a time of change from the low-resistance state to the high-resistance state differ from each other. A reading signal for detecting the resistance value of the recording layer in the variable resistance element is applied with a polarity of one of the threshold values of the applied signals which one has a higher absolute value and with a value lower than the absolute value.
摘要翻译：本发明提供了一种存储装置，包括在两个电极之间具有记录层的可变电阻元件。在可变电阻元件中，通过向两个电极施加不同极性的电位，记录层的电阻值被可逆地改变为高电阻状态的值和低电阻状态的值之一。从高电阻状态向低电阻状态变化时的施加信号的阈值的绝对值和从低电阻变化时的施加信号的阈值的绝对值状态到高电阻状态彼此不同。用于检测可变电阻元件中的记录层的电阻值的读取信号以一个具有较高绝对值并且具有低于绝对值的值的施加信号的阈值之一的极性被施加。

20. 发明申请

US20060067114A1 Storage apparatus and semiconductor apparatus 有权
标题翻译：存储装置和半导体装置
公开(公告)号：US20060067114A1
公开(公告)日：2006-03-30
申请号：US11225593
申请日：2005-09-13
申请人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
发明人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
IPC分类号： G11C11/00
CPC分类号： G11C13/02 , G11C13/0069 , G11C2213/79
摘要： A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.
摘要翻译：一种存储装置，具有各自具有存储元件的存储器件，该存储元件具有不低于第一阈值信号的电信号的施加使得存储元件从高电阻值状态向低电阻值状态移动的特征，施加不低于第一阈值信号极性的第二阈值信号的电信号允许存储元件从低电阻值状态移位到高电阻值状态，并且连接的电路元件将串联的存储元件作为负载; 其中所述存储器件被布置在矩阵中，并且每个所述存储器件的一个端子连接到公共线; 并且其中电源电位和接地电位之间的中间电位被施加到公共线。

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