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11. 发明申请

US20060131653A1 CMOS thin film transistor comprising common gate, logic device comprising the CMOS thin film transistor, and method of manufacturing the CMOS thin film transistor 有权
标题翻译：包括公共栅极的CMOS薄膜晶体管，包括CMOS薄膜晶体管的逻辑器件和制造CMOS薄膜晶体管的方法
公开(公告)号：US20060131653A1
公开(公告)日：2006-06-22
申请号：US11305394
申请日：2005-12-16
申请人： Moon-Kyung Kim , Jo-Won Lee , Yoon-Dong Park , Chung-Woo Kim
发明人： Moon-Kyung Kim , Jo-Won Lee , Yoon-Dong Park , Chung-Woo Kim
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203
摘要： A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer formed on the base substrate. A PMOS transistor and an NMOS transistor are formed on a single semiconductor layer to intersect each other, and a common gate is formed on the intersection area. In addition, a Schottky barrier inducing material layer is formed on a source and a drain of the PMOS transistor.
摘要翻译：提供了包括公共栅极的互补金属氧化物半导体（CMOS）薄膜晶体管，包括CMOS薄膜晶体管的逻辑器件和制造CMOS薄膜晶体管的方法。在一个实施例中，CMOS薄膜晶体管包括基底基板和形成在基底基板上的半导体层。 PMOS晶体管和NMOS晶体管形成在单个半导体层上以彼此相交，并且在交叉区域上形成公共栅极。此外，在PMOS晶体管的源极和漏极上形成肖特基势垒诱导材料层。

12. 发明授权

US06479365B2 Single electron transistor using porous silicon and manufacturing method thereof 有权
标题翻译：使用多孔硅的单电子晶体管及其制造方法
公开(公告)号：US06479365B2
公开(公告)日：2002-11-12
申请号：US10090169
申请日：2002-03-05
申请人： Jo-won Lee , Chung-woo Kim , Byong-man Kim , Moon-kyung Kim
发明人： Jo-won Lee , Chung-woo Kim , Byong-man Kim , Moon-kyung Kim
IPC分类号： H01L2176
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/16 , Y10S438/96 , Y10S977/937
摘要： A single electron transistor using porous silicon, which is fabricated by applying porous silicon having a size of several tens of nanometers obtained by electrochemically etching silicon, and a fabrication method thereof, are provided. In the single electron transistor using porous silicon, silicon pores, each of which has a diameter of 5 nm or less, are fabricated by electrochemically etching a silicon on insulator (SOI) substrate having silicon dioxide (SiO2) in its lower portion using an HF-based solution, and serve as islands of a single electron transistor. Also, a source and a drain are formed of silicon on which metal is deposited or silicon doped with impurities. Hence, formation of islands and tunnel barriers is easy, mass production is possible, and the sizes of islands can be controlled by oxidation, so that single electron transistors capable of operating at room temperature can be easily fabricated.
摘要翻译：提供了通过使用通过电化学蚀刻硅获得的尺寸为几十纳米的多孔硅制造的使用多孔硅的单电子晶体管及其制造方法。在使用多孔硅的单电子晶体管中，通过使用HF在其下部电化学蚀刻其下部具有二氧化硅（SiO 2）的绝缘体上硅（SOI）衬底，制造每个具有5nm或更小直径的硅孔。的溶液，并且用作单电子晶体管的岛。此外，源极和漏极由其上沉积有金属的硅或掺杂有杂质的硅形成。因此，岛和隧道壁垒的形成是容易的，批量生产是可能的，并且可以通过氧化来控制岛的尺寸，使得能够容易地制造能够在室温下操作的单电子晶体管。

13. 发明授权

US08843854B2 Method for executing menu in mobile terminal and mobile terminal using the same 有权
标题翻译：用于在移动终端和使用其的移动终端中执行菜单的方法
公开(公告)号：US08843854B2
公开(公告)日：2014-09-23
申请号：US12778984
申请日：2010-05-12
申请人： Se Sook Oh , Ho Jae Jung , Moon Kyung Kim
发明人： Se Sook Oh , Ho Jae Jung , Moon Kyung Kim
IPC分类号： G06F3/048 , G06F3/0488 , G06F3/0482
CPC分类号： G06F3/04883 , G06F3/0482
摘要： A method for executing a menu in a mobile terminal is disclosed, wherein the method includes displaying a first icon on a touch screen of the mobile terminal, receiving a first multi touch gesture pattern on the first icon, and displaying at least one second icon upon recognition of the first multi-gesture pattern, the at least one second icon a sub icon of the first icon.
摘要翻译：公开了一种用于在移动终端中执行菜单的方法，其中所述方法包括在所述移动终端的触摸屏上显示第一图标，在所述第一图标上接收第一多点触摸手势图案，以及在所述第一图标上显示至少一个第二图标所述第一多姿势图案的识别，所述至少一个第二图标是所述第一图标的子图标。

14. 发明授权

US07426031B2 Method and apparatus for inspecting target defects on a wafer 有权
标题翻译：用于检查晶片上的目标缺陷的方法和装置
公开(公告)号：US07426031B2
公开(公告)日：2008-09-16
申请号：US11461726
申请日：2006-08-01
申请人： Moon-Kyung Kim , Chung-Sam Jun , Yu-Sin Yang
发明人： Moon-Kyung Kim , Chung-Sam Jun , Yu-Sin Yang
IPC分类号： G01B9/08 , G01N21/00
CPC分类号： G01N21/9501
摘要： A defect inspecting apparatus includes a first support unit supporting a standard sample having standard defects, a second support unit supporting a wafer having target defects, a light source irradiating an incident light to the standard sample or the wafer, a light receiving part collecting reflection light reflected from the standard sample and the wafer, a detection part detecting the standard defects and the target defects by using the reflection light, a comparing part comparing information obtained using the reflection light reflected from the standard sample with a predetermined standard information of the standard defects to confirm a reliability of a step for detecting the target defects and a determination portion determining whether the step is allowed to be performed or not.
摘要翻译：缺陷检查装置包括支撑具有标准缺陷的标准样品的第一支撑单元，支撑具有目标缺陷的晶片的第二支撑单元，向标准样品或晶片照射入射光的光源，收集反射光的光接收部从标准样品和晶片反射的检测部分，通过使用反射光检测标准缺陷和目标缺陷的检测部分，将使用从标准样品反射的反射光获得的信息与标准缺陷的预定标准信息进行比较的比较部分以确认用于检测目标缺陷的步骤的可靠性，并且确定部分确定是否允许执行该步骤。

15. 发明申请

US20070138541A1 Method of erasing data from SONOS memory device 审中-公开
标题翻译：从SONOS存储器件擦除数据的方法
公开(公告)号：US20070138541A1
公开(公告)日：2007-06-21
申请号：US11702064
申请日：2007-02-05
申请人： Soo-doo Chae , Chung-woo Kim , Jo-won Lee , Moon-kyung Kim
发明人： Soo-doo Chae , Chung-woo Kim , Jo-won Lee , Moon-kyung Kim
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0466
摘要： A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.
摘要翻译： SONOS存储器件和从其中擦除数据的方法包括将第二符号的电荷载体注入陷阱膜，捕获膜俘获第一符号的电荷载体以在其中存储数据。第二符号的电荷载体由形成在与至少一个位线接触的第一和第二电极中的一个与接触字线的栅电极之间的电场产生。可以在栅电极和捕获膜之间设置阻挡膜。第二标志的电荷载体可能是热孔。这种擦除提高了擦除速度，从而提高了SONOS存储器件的性能。

16. 发明申请

US20110049650A1 Electro-Mechanical Transistor 有权
标题翻译：机电晶体管
公开(公告)号：US20110049650A1
公开(公告)日：2011-03-03
申请号：US12549906
申请日：2009-08-28
申请人： Sandip Tiwari , Moon-Kyung Kim , Joshua Mark Rubin , Soo-Doo Chae , Choong-Man Lee , Ravishankar Sundararaman
发明人： Sandip Tiwari , Moon-Kyung Kim , Joshua Mark Rubin , Soo-Doo Chae , Choong-Man Lee , Ravishankar Sundararaman
IPC分类号： H01L29/84
CPC分类号： H01L49/00 , B82Y10/00 , G11C13/025 , G11C23/00
摘要： An electromechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.
摘要翻译：机电晶体管包括彼此间隔开的源电极和漏电极。源极柱位于衬底和源电极之间。漏极柱位于衬底和漏电极之间。可移动通道与源电极和漏电极间隔开。门纳米柱位于可移动通道和基板之间。第一电介质层位于可移动沟道和栅极纳米柱之间。第二电介质层位于源极柱和源极之间。第三介电层位于漏极柱和漏极之间。

17. 发明申请

US20090010058A1 MULTI-BIT NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND METHOD OF FABRICATING THE SAME 失效
标题翻译：多位非易失性存储器件，其操作方法及其制造方法
公开(公告)号：US20090010058A1
公开(公告)日：2009-01-08
申请号：US12209735
申请日：2008-09-12
申请人： Soo-doo CHAE , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
发明人： Soo-doo CHAE , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0475 , H01L21/28282 , H01L29/66833 , H01L29/7923
摘要： A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.
摘要翻译：可以提供多位非易失性存储器件及其操作和制造方法。存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。

18. 发明授权

US07271890B2 Method and apparatus for inspecting defects 失效
标题翻译：检查缺陷的方法和装置
公开(公告)号：US07271890B2
公开(公告)日：2007-09-18
申请号：US10903852
申请日：2004-07-30
申请人： Joung-Soo Kim , Yu-Sin Yang , Moon-Kyung Kim , Sang-Mun Chon , Sun-Yong Choi , Chung-Sam Jun
发明人： Joung-Soo Kim , Yu-Sin Yang , Moon-Kyung Kim , Sang-Mun Chon , Sun-Yong Choi , Chung-Sam Jun
IPC分类号： G01N21/00
CPC分类号： G01N21/9501 , G01N21/55
摘要： In a method for inspecting a defect in accordance with one aspect of the present invention, an object is divided into a plurality of regions. Reflectivity of each of the plurality of regions is obtained. Amplification ratio for each region is determined using the reflectivity. A light is irradiated onto the regions. A light reflected from a first region is amplified by a first amplification ratio that is determined for the first region. Moving the irradiated light from the first region to a second region is detected. A light reflected from the second region is amplified by a second amplification ratio that is determined for the second region. The amplified lights from the first region and the second region are analyzed to determine an existence of a defect on the object.
摘要翻译：在根据本发明的一个方面的用于检查缺陷的方法中，对象被分成多个区域。获得多个区域中的每一个的反射率。使用反射率确定每个区域的放大率。光照射到这些区域上。从第一区域反射的光被第一区域确定的第一放大率放大。检测到将照射的光从第一区域移动到第二区域。从第二区域反射的光被第二区域确定的第二放大率放大。分析来自第一区域和第二区域的放大的光以确定物体上存在缺陷。

19. 发明授权

US07187030B2 SONOS memory device 有权
标题翻译： SONOS存储设备
公开(公告)号：US07187030B2
公开(公告)日：2007-03-06
申请号：US10867706
申请日：2004-06-16
申请人： Soo-doo Chae , Chung-woo Kim , Jo-won Lee , Moon-kyung Kim
发明人： Soo-doo Chae , Chung-woo Kim , Jo-won Lee , Moon-kyung Kim
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0466
摘要： A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.
摘要翻译： SONOS存储器件和从其中擦除数据的方法包括将第二符号的电荷载体注入陷阱膜，捕获膜俘获第一符号的电荷载体以在其中存储数据。第二符号的电荷载体由形成在与至少一个位线接触的第一和第二电极中的一个与接触字线的栅电极之间的电场产生。可以在栅电极和捕获膜之间设置阻挡膜。第二标志的电荷载体可能是热孔。这种擦除提高了擦除速度，从而提高了SONOS存储器件的性能。

20. 发明授权

US08080839B2 Electro-mechanical transistor 有权
标题翻译：机电晶体管
公开(公告)号：US08080839B2
公开(公告)日：2011-12-20
申请号：US12549906
申请日：2009-08-28
申请人： Sandip Tiwari , Moon-Kyung Kim , Joshua Mark Rubin , Soo-Doo Chae , Choong-Man Lee , Ravishankar Sundararaman
发明人： Sandip Tiwari , Moon-Kyung Kim , Joshua Mark Rubin , Soo-Doo Chae , Choong-Man Lee , Ravishankar Sundararaman
IPC分类号： H01L29/84
CPC分类号： H01L49/00 , B82Y10/00 , G11C13/025 , G11C23/00
摘要： An electro-mechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.
摘要翻译：机电晶体管包括彼此间隔开的源电极和漏电极。源极柱位于衬底和源电极之间。漏极柱位于衬底和漏电极之间。可移动通道与源电极和漏电极间隔开。门纳米柱位于可移动通道和基板之间。第一电介质层位于可移动沟道和栅极纳米柱之间。第二电介质层位于源极柱和源极之间。第三介电层位于漏极柱和漏极之间。

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