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1. 发明申请

US20070030478A1 METHOD AND APPARATUS FOR INSPECTING TARGET DEFECTS ON A WAFER 有权
标题翻译：用于检测波峰的目标缺陷的方法和装置
公开(公告)号：US20070030478A1
公开(公告)日：2007-02-08
申请号：US11461726
申请日：2006-08-01
申请人： Moon-Kyung KIM , Chung-Sam JUN , Yu-Sin YANG
发明人： Moon-Kyung KIM , Chung-Sam JUN , Yu-Sin YANG
IPC分类号： G01N21/88
CPC分类号： G01N21/9501
摘要： A defect inspecting apparatus includes a first support unit supporting a standard sample having standard defects, a second support unit supporting a wafer having target defects, a light source irradiating an incident light to the standard sample or the wafer, a light receiving part collecting reflection light reflected from the standard sample and the wafer, a detection part detecting the standard defects and the target defects by using the reflection light, a comparing part comparing information obtained using the reflection light reflected from the standard sample with a predetermined standard information of the standard defects to confirm a reliability of a step for detecting the target defects and a determination portion determining whether the step is allowed to be performed or not.
摘要翻译：缺陷检查装置包括支撑具有标准缺陷的标准样品的第一支撑单元，支撑具有目标缺陷的晶片的第二支撑单元，向标准样品或晶片照射入射光的光源，收集反射光的光接收部从标准样品和晶片反射的检测部分，通过使用反射光检测标准缺陷和目标缺陷的检测部分，将使用从标准样品反射的反射光获得的信息与标准缺陷的预定标准信息进行比较的比较部分以确认用于检测目标缺陷的步骤的可靠性，并且确定部分确定是否允许执行该步骤。

2. 发明申请

US20050112815A1 Silicon-oxide-nitride-oxide-silicon (SONOS) memory device and methods of manufacturing and operating the same 有权
标题翻译：氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造和操作的方法
公开(公告)号：US20050112815A1
公开(公告)日：2005-05-26
申请号：US10961481
申请日：2004-10-12
申请人： Moon-kyung Kim , Chung-woo Kim , Jo-won Lee , Eun-hong Lee , Hee-soon Chae
发明人： Moon-kyung Kim , Chung-woo Kim , Jo-won Lee , Eun-hong Lee , Hee-soon Chae
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/02 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/8239 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475 , H01L21/28282 , H01L29/66833 , H01L29/792
摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device, and a lower stack structure formed under the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device.
摘要翻译：在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造和操作方法中，SONOS存储器件包括包括源极和漏极区域以及沟道区域的半导体层，上部堆叠结构形成在半导体层，上层堆叠结构和形成上SONOS存储器件的半导体层，以及形成在半导体层下的下堆叠结构，下堆叠结构和半导体层形成下SONOS存储器件。

3. 发明申请

US20050094137A1 Method and apparatus for inspecting defects 失效
标题翻译：检查缺陷的方法和装置
公开(公告)号：US20050094137A1
公开(公告)日：2005-05-05
申请号：US10903852
申请日：2004-07-30
申请人： Joung-Soo Kim , Yu-Sin Yang , Moon-Kyung Kim , Sang-Mun Chon , Sun-Yong Choi , Chung-Sam Jun
发明人： Joung-Soo Kim , Yu-Sin Yang , Moon-Kyung Kim , Sang-Mun Chon , Sun-Yong Choi , Chung-Sam Jun
IPC分类号： H01L21/66 , G01N21/00 , G01N21/55 , G01N21/95
CPC分类号： G01N21/9501 , G01N21/55
摘要： In a method for inspecting a defect in accordance with one aspect of the present invention, an object is divided into a plurality of regions. Reflectivity of each of the plurality of regions is obtained. Amplification ratio for each region is determined using the reflectivity. A light is irradiated onto the regions. A light reflected from a first region is amplified by a first amplification ratio that is determined for the first region. Moving the irradiated light from the first region to a second region is detected. A light reflected from the second region is amplified by a second amplification ratio that is determined for the second region. The amplified lights from the first region and the second region are analyzed to determine an existence of a defect on the object.
摘要翻译：在根据本发明的一个方面的用于检查缺陷的方法中，对象被分成多个区域。获得多个区域中的每一个的反射率。使用反射率确定每个区域的放大率。光照射到这些区域上。从第一区域反射的光被第一区域确定的第一放大率放大。检测到将照射的光从第一区域移动到第二区域。从第二区域反射的光被第二区域确定的第二放大率放大。分析来自第一区域和第二区域的放大的光以确定物体上存在缺陷。

4. 发明授权

US06670670B2 Single electron memory device comprising quantum dots between gate electrode and single electron storage element and method for manufacturing the same 有权
公开(公告)号：US06670670B2
公开(公告)日：2003-12-30
申请号：US10125597
申请日：2002-04-19
申请人： Soo-doo Chae , Byong-man Kim , Moon-kyung Kim , Hee-soon Chae , Won-il Ryu
发明人： Soo-doo Chae , Byong-man Kim , Moon-kyung Kim , Hee-soon Chae , Won-il Ryu
IPC分类号： H01L29788
CPC分类号： B82Y10/00 , G11C2216/08 , H01L21/28273 , H01L29/7888
摘要： A single electron memory device including quantum dots between a gate electrode and a single electron storage element and a method for manufacturing the same, wherein the single electron memory device includes a substrate on which a nano-scale channel region is formed between a source and a drain, and a gate lamination pattern including quantum dots on the channel region. The gate lamination pattern includes a lower layer formed on the channel region, a single electron storage medium storing a single electron tunneling through the lower layer formed on the lower layer, an upper layer including quantum dots formed on the single electron storage medium, and a gate electrode formed on the upper layer to be in contact with the quantum dots.

5. 发明申请

US20100299635A1 METHOD FOR EXECUTING MENU IN MOBILE TERMINAL AND MOBILE TERMINAL USING THE SAME 有权
标题翻译：使用移动终端和移动终端执行菜单的方法
公开(公告)号：US20100299635A1
公开(公告)日：2010-11-25
申请号：US12778984
申请日：2010-05-12
申请人： Se Sook Oh , Ho Jae Jung , Moon Kyung Kim
发明人： Se Sook Oh , Ho Jae Jung , Moon Kyung Kim
IPC分类号： G06F3/048 , G06F3/033
CPC分类号： G06F3/04883 , G06F3/0482
摘要： A method for executing a menu in a mobile terminal is disclosed, wherein the method includes displaying a first icon on a touch screen of the mobile terminal, receiving a first multi touch gesture pattern on the first icon, and displaying at least one second icon upon recognition of the first multi-gesture pattern, the at least one second icon a sub icon of the first icon.
摘要翻译：公开了一种用于在移动终端中执行菜单的方法，其中所述方法包括在所述移动终端的触摸屏上显示第一图标，在所述第一图标上接收第一多点触摸手势图案，以及在所述第一图标上显示至少一个第二图标所述第一多姿势图案的识别，所述至少一个第二图标是所述第一图标的子图标。

6. 发明申请

US20090068808A1 Method of manufacturing a nonvolatile semiconductor memory device having a gate stack 审中-公开
标题翻译：制造具有栅叠层的非易失性半导体存储器件的方法
公开(公告)号：US20090068808A1
公开(公告)日：2009-03-12
申请号：US12230423
申请日：2008-08-28
申请人： Soo-doo Chae , Chung-woo Kim , Jung-hyun Lee , Moon-kyung Kim , Hyun-sang Hwang
发明人： Soo-doo Chae , Chung-woo Kim , Jung-hyun Lee , Moon-kyung Kim , Hyun-sang Hwang
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28194 , H01L27/11568 , H01L29/40117 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66833
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si3N4); a first insulating film having a higher dielectric constant than a nitride film; and a gate electrode. Such a nonvolatile semiconductor memory device can effectively control the trap density according to the doping concentration, thereby increasing the write/erase speed of data at a low operating voltage.
摘要翻译：非易失性半导体存储器件包括具有源极区和漏极区的半导体衬底，以及形成在半导体衬底上并与源极和漏极区接触的栅堆叠。栅极堆叠从衬底依次顺序包括：隧道膜; 掺杂有第一预定杂质的第一捕获材料膜，所述第一捕获材料膜具有比所述氮化物膜（Si 3 N 4）更高的介电常数; 具有比氮化膜更高的介电常数的第一绝缘膜; 和栅电极。这种非易失性半导体存储器件可以根据掺杂浓度有效地控制阱密度，从而在低工作电压下增加数据的写入/擦除速度。

7. 发明授权

US07432554B2 CMOS thin film transistor comprising common gate, logic device comprising the CMOS thin film transistor, and method of manufacturing the CMOS thin film transistor 有权
标题翻译：包括公共栅极的CMOS薄膜晶体管，包括CMOS薄膜晶体管的逻辑器件和制造CMOS薄膜晶体管的方法
公开(公告)号：US07432554B2
公开(公告)日：2008-10-07
申请号：US11305394
申请日：2005-12-16
申请人： Moon-Kyung Kim , Jo-Won Lee , Yoon-Dong Park , Chung-Woo Kim
发明人： Moon-Kyung Kim , Jo-Won Lee , Yoon-Dong Park , Chung-Woo Kim
IPC分类号： H01L27/08
CPC分类号： H01L21/84 , H01L27/1203
摘要： A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer formed on the base substrate. A PMOS transistor and an NMOS transistor are formed on a single semiconductor layer to intersect each other, and a common gate is formed on the intersection area. In addition, a Schottky barrier inducing material layer is formed on a source and a drain of the PMOS transistor.
摘要翻译：提供了包括公共栅极的互补金属氧化物半导体（CMOS）薄膜晶体管，包括CMOS薄膜晶体管的逻辑器件和制造CMOS薄膜晶体管的方法。在一个实施例中，CMOS薄膜晶体管包括基底基板和形成在基底基板上的半导体层。 PMOS晶体管和NMOS晶体管形成在单个半导体层上以彼此相交，并且在交叉区域上形成公共栅极。此外，在PMOS晶体管的源极和漏极上形成肖特基势垒诱导材料层。

8. 发明授权

US07420256B2 Nonvolatile semiconductor memory device having a gate stack and method of manufacturing the same 有权
标题翻译：具有栅极堆叠的非易失性半导体存储器件及其制造方法
公开(公告)号：US07420256B2
公开(公告)日：2008-09-02
申请号：US10835097
申请日：2004-04-30
申请人： Soo-doo Chae , Chung-woo Kim , Jung-hyun Lee , Moon-kyung Kim , Hyun-sang Hwang
发明人： Soo-doo Chae , Chung-woo Kim , Jung-hyun Lee , Moon-kyung Kim , Hyun-sang Hwang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28194 , H01L21/28282 , H01L27/11568 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66833
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si3N4); a first insulating film having a higher dielectric constant than a nitride film; and a gate electrode. Such a nonvolatile semiconductor memory device can effectively control the trap density according to the doping concentration, thereby increasing the write/erase speed of data at a low operating voltage.
摘要翻译：非易失性半导体存储器件包括具有源极区和漏极区的半导体衬底，以及形成在半导体衬底上并与源极和漏极区接触的栅堆叠。栅极堆叠从衬底依次顺序包括：隧道膜; 掺杂有第一预定杂质的第一捕获材料膜，所述第一捕获材料膜具有比所述氮化物膜（Si 3 N 4 N 4）更高的介电常数; 具有比氮化膜更高的介电常数的第一绝缘膜; 和栅电极。这种非易失性半导体存储器件可以根据掺杂浓度有效地控制阱密度，从而在低工作电压下增加数据的写入/擦除速度。

9. 发明授权

US07310140B2 Method and apparatus for inspecting a wafer surface 有权
标题翻译：检查晶片表面的方法和装置
公开(公告)号：US07310140B2
公开(公告)日：2007-12-18
申请号：US10877684
申请日：2004-06-25
申请人： Tae-Min Eom , Yu-Sin Yang , Chung-Sam Jun , Yun-Jung Jee , Joung-Soo Kim , Moon-Kyung Kim , Sang-Mun Chon , Sun-Yong Choi
发明人： Tae-Min Eom , Yu-Sin Yang , Chung-Sam Jun , Yun-Jung Jee , Joung-Soo Kim , Moon-Kyung Kim , Sang-Mun Chon , Sun-Yong Choi
IPC分类号： G01N21/00
CPC分类号： G01N21/9501 , G01N21/47 , G01N21/55 , G01N2021/556
摘要： In a method and an apparatus for inspecting a wafer surface, a wafer is loaded into a chamber. An incident light including a first light for sensing a vertical position of the wafer and a second light for inspecting the wafer surface is irradiated onto the wafer. The first light is reflected on an inspection region or a next inspection region of the wafer and is detected to control a wafer position. The second light is scattered on the inspection region and is detected to inspect the wafer surface of the inspection region. Position information of a wafer is examined and a position of the wafer is adjusted before inspecting a surface of inspection region of a wafer so as to enable accurate inspection of the wafer surface.
摘要翻译：在用于检查晶片表面的方法和装置中，将晶片装入室中。将包括用于感测晶片的垂直位置的第一光和用于检查晶片表面的第二光的入射光照射到晶片上。第一光被反射在晶片的检查区域或下一个检查区域上，并被检测以控制晶片位置。第二光被分散在检查区域上，并被检测以检查检查区域的晶片表面。在检查晶片的检查区域的表面之前检查晶片的位置信息并调整晶片的位置，以便能够精确地检查晶片表面。

10. 发明申请

US20060255399A1 Nonvolatile memory device having a plurality of trapping films 审中-公开
标题翻译：具有多个捕获膜的非易失性存储器件
公开(公告)号：US20060255399A1
公开(公告)日：2006-11-16
申请号：US11354076
申请日：2006-02-15
申请人： Ju-Hyung Kim , Jeong-Hee Han , Chung-Woo Kim , Yo-Sep Min , Moon-Kyung Kim , Youn-Seok Jeong
发明人： Ju-Hyung Kim , Jeong-Hee Han , Chung-Woo Kim , Yo-Sep Min , Moon-Kyung Kim , Youn-Seok Jeong
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , H01L29/4232 , H01L29/42324 , H01L29/513 , H01L29/792
摘要： Provided is a nonvolatile memory device which includes a tunneling insulating film formed on a semiconductor substrate, a storage node formed on the tunneling insulating film, a blocking insulating film formed on the storage node, and a control gate electrode formed on the blocking insulating film. The storage node includes at least two trapping films having different trap densities, and the blocking insulating film has a dielectric constant greater than that of the silicon oxide film.
摘要翻译：提供了一种非易失性存储器件，其包括形成在半导体衬底上的隧道绝缘膜，形成在隧道绝缘膜上的存储节点，形成在存储节点上的阻挡绝缘膜，以及形成在阻挡绝缘膜上的控制栅电极。存储节点包括具有不同陷阱密度的至少两个俘获膜，并且阻挡绝缘膜的介电常数大于氧化硅膜的介电常数。

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