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1. 发明授权

US08237214B2 Non-volatile memory device including metal-insulator transition material 失效
标题翻译：包括金属 - 绝缘体过渡材料的非易失性存储器件
公开(公告)号：US08237214B2
公开(公告)日：2012-08-07
申请号：US11980352
申请日：2007-10-31
申请人： Wan-jun Park , Jo-won Lee , Sang-hun Jeon , Chung-woo Kim
发明人： Wan-jun Park , Jo-won Lee , Sang-hun Jeon , Chung-woo Kim
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , H01L21/28282
摘要： A non-volatile memory device including a metal-insulator transition (MIT) material is provided. The non-volatile memory device includes a gate stack having a tunneling layer, a charge trap layer, a blocking layer and a gate electrode formed on a substrate, wherein at least one of the tunneling layer and the blocking layer is formed of an MIT (metal-insulator transition) material.
摘要翻译：提供了包括金属 - 绝缘体转变（MIT）材料的非易失性存储器件。非易失性存储器件包括具有隧道层，电荷陷阱层，形成在衬底上的阻挡层和栅电极的栅极堆叠，其中隧道层和阻挡层中的至少一个由MIT形成金属 - 绝缘体转变）材料。

2. 发明授权

US07759196B2 Multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same 失效
标题翻译：多位非易失性存储器件，其操作方法及其制造方法
公开(公告)号：US07759196B2
公开(公告)日：2010-07-20
申请号：US12209735
申请日：2008-09-12
申请人： Soo-doo Chae , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
发明人： Soo-doo Chae , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： G11C16/0475 , H01L21/28282 , H01L29/66833 , H01L29/7923
摘要： A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.
摘要翻译：可以提供多位非易失性存储器件及其操作和制造方法。存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。

3. 发明授权

US07719871B2 Methods of operating and manufacturing logic device and semiconductor device including complementary nonvolatile memory device, and reading circuit for the same 有权
标题翻译：逻辑器件和半导体器件的操作和制造方法包括互补的非易失性存储器件和用于其的读取电路
公开(公告)号：US07719871B2
公开(公告)日：2010-05-18
申请号：US12025372
申请日：2008-02-04
申请人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
发明人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
IPC分类号： G11C5/06
CPC分类号： G11C11/5621 , H01L27/0688 , H01L27/11521 , H01L27/11551
摘要： Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
摘要翻译：提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。第一和第二非易失性存储器被布置成使得其上表面相邻。

4. 发明申请

US20080212376A1 METHODS OF OPERATING AND MANUFACTURING LOGIC DEVICE AND SEMICONDUCTOR DEVICE INCLUDING COMPLEMENTARY NONVOLATILE MEMORY DEVICE, AND READING CIRCUIT FOR THE SAME 有权
标题翻译：操作和制造逻辑器件和包括补充非易失性存储器件的半导体器件的方法及其读取电路
公开(公告)号：US20080212376A1
公开(公告)日：2008-09-04
申请号：US12025372
申请日：2008-02-04
申请人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
发明人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
IPC分类号： G11C16/06 , H01L21/336 , G11C7/00
CPC分类号： G11C11/5621 , H01L27/0688 , H01L27/11521 , H01L27/11551
摘要： Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
摘要翻译：提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。第一和第二非易失性存储器被布置成使得其上表面相邻。

5. 发明申请

US20080157186A1 Non-volatile memory device including metal-insulator transition material 失效
标题翻译：包括金属 - 绝缘体过渡材料的非易失性存储器件
公开(公告)号：US20080157186A1
公开(公告)日：2008-07-03
申请号：US11980352
申请日：2007-10-31
申请人： Wan-jun Park , Jo-won Lee , Sang-hun Jeon , Chung-woo Kim
发明人： Wan-jun Park , Jo-won Lee , Sang-hun Jeon , Chung-woo Kim
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , H01L21/28282
摘要： A non-volatile memory device including a metal-insulator transition (MIT) material is provided. The non-volatile memory device includes a gate stack having a tunneling layer, a charge trap layer, a blocking layer and a gate electrode formed on a substrate, wherein at least one of the tunneling layer and the blocking layer is formed of an MIT (metal-insulator transition) material.
摘要翻译：提供了包括金属 - 绝缘体转变（MIT）材料的非易失性存储器件。非易失性存储器件包括具有隧道层，电荷陷阱层，形成在衬底上的阻挡层和栅电极的栅极堆叠，其中隧道层和阻挡层中的至少一个由MIT形成金属 - 绝缘体转变）材料。

6. 发明授权

US07202521B2 Silicon-oxide-nitride-oxide-silicon (SONOS) memory device and methods of manufacturing and operating the same 有权
标题翻译：氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造和操作的方法
公开(公告)号：US07202521B2
公开(公告)日：2007-04-10
申请号：US10961481
申请日：2004-10-12
申请人： Moon-kyung Kim , Chung-woo Kim , Jo-won Lee , Eun-hong Lee , Hee-soon Chae
发明人： Moon-kyung Kim , Chung-woo Kim , Jo-won Lee , Eun-hong Lee , Hee-soon Chae
IPC分类号： H01L29/76
CPC分类号： G11C16/0475 , H01L21/28282 , H01L29/66833 , H01L29/792
摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device, and a lower stack structure formed under the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device.
摘要翻译：在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造和操作方法中，SONOS存储器件包括包括源极和漏极区域以及沟道区域的半导体层，上部堆叠结构形成在半导体层，上层堆叠结构和形成上SONOS存储器件的半导体层，以及形成在半导体层下的下堆叠结构，下堆叠结构和半导体层形成下SONOS存储器件。

7. 发明申请

US20060180853A1 SONOS memory device having side gate stacks and method of manufacturing the same 有权
标题翻译：具有侧栅叠层的SONOS存储器件及其制造方法
公开(公告)号：US20060180853A1
公开(公告)日：2006-08-17
申请号：US11200153
申请日：2005-08-10
申请人： Won-il Ryu , Jo-won Lee , Se-wook Yoon , Chung-woo Kim
发明人： Won-il Ryu , Jo-won Lee , Se-wook Yoon , Chung-woo Kim
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/7881 , H01L29/792 , H01L29/7923
摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.
摘要翻译：在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造方法中，SONOS存储器件包括半导体衬底，沉积在半导体衬底上的绝缘层，形成在预定区域上的有源层并且被分成源区域，漏极区域和沟道区域，形成在沟道区域的第一侧的第一侧栅叠层和形成在沟道区域的第二侧的第二侧栅叠层与通道区域的第一侧相对。在SONOS存储器件中，可以在每个SONOS存储器件中存储至少两位数据，从而允许半导体存储器件的集成密度增加而不增加其面积。

8. 发明申请

US20060108629A1 Multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same 审中-公开
标题翻译：多位非易失性存储器件，其操作方法及其制造方法
公开(公告)号：US20060108629A1
公开(公告)日：2006-05-25
申请号：US11220619
申请日：2005-09-08
申请人： Soo-doo Chae , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
发明人： Soo-doo Chae , Moon-kyung Kim , Jo-won Lee , Chung-woo Kim
IPC分类号： H01L29/788
CPC分类号： G11C16/0475 , H01L29/40117 , H01L29/66833 , H01L29/7923
摘要： A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.
摘要翻译：可以提供多位非易失性存储器件及其操作和制造方法。存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。

9. 发明授权

US06597036B1 Multi-value single electron memory using double-quantum dot and driving method thereof 失效
标题翻译：使用双量子点的多值单电子存储器及其驱动方法
公开(公告)号：US06597036B1
公开(公告)日：2003-07-22
申请号：US09692620
申请日：2000-10-20
申请人： Jo-won Lee , Byong-man Kim , Moon-kyung Kim
发明人： Jo-won Lee , Byong-man Kim , Moon-kyung Kim
IPC分类号： H01L29788
CPC分类号： B82Y10/00 , G11C11/56 , G11C2216/08 , H01L21/28273 , H01L29/66825 , H01L29/7887 , H01L29/7888
摘要： A multi-value single electron memory using a multi-quantum dot, in which the floating gates (FG) of a EEPROM or a flash memory are formed to act as two quantum dots, and the two quantum dots are applied to multi-value memories, and a driving method of the multi-value single electron memory, are provided. Thus, a multi-value memory can be realized using two quantum dots. Also, an ultra-highly integrated memory of 1 Tb or greater can be realized without encountering a physical limit such as a short channel effect (SCE) caused by scaling down MOSFETs, in contrast to other memories.
摘要翻译：使用多量子点的多值单电子存储器，其中形成EEPROM或闪存的浮动栅极（FG）作为两个量子点，并且将两个量子点应用于多值存储器，以及多值单电子存储器的驱动方法。因此，可以使用两个量子点来实现多值存储器。此外，与其他存储器相反，可以实现1Tb或更大的超高度集成存储器，而不会遇到由缩小MOSFET引起的短沟道效应（SCE）等物理限制。

10. 发明授权

US06414333B1 Single electron transistor using porous silicon 有权
标题翻译：单电子晶体管采用多孔硅
公开(公告)号：US06414333B1
公开(公告)日：2002-07-02
申请号：US09522603
申请日：2000-03-10
申请人： Jo-won Lee , Chung-woo Kim , Byong-man Kim , Moon-kyung Kim
发明人： Jo-won Lee , Chung-woo Kim , Byong-man Kim , Moon-kyung Kim
IPC分类号： H01L2906
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/16 , Y10S438/96 , Y10S977/937
摘要： A single electron transistor using porous silicon, which is fabricated by applying porous silicon having a size of several tens of nanometers obtained by electrochemically etching silicon, and a fabrication method thereof, are provided. In the single electron transistor using porous silicon, silicon pores, each of which has a diameter of 5 nm or less, are fabricated by electrochemically etching a silicon on insulator (SOI) substrate having silicon dioxide (SiO2) in its lower portion using an HF-based solution, and serve as islands of a single electron transistor. Also, a source and a drain are formed of silicon on which metal is deposited or silicon doped with impurities. Hence, formation of islands and tunnel barriers is easy, mass production is possible, and the sizes of islands can be controlled by oxidation, so that single electron transistors capable of operating at room temperature can be easily fabricated.
摘要翻译：提供了通过使用通过电化学蚀刻硅获得的尺寸为几十纳米的多孔硅制造的使用多孔硅的单电子晶体管及其制造方法。在使用多孔硅的单电子晶体管中，通过使用HF在其下部电化学蚀刻其下部具有二氧化硅（SiO 2）的绝缘体上硅（SOI）衬底，制造每个具有5nm或更小直径的硅孔。的溶液，并且用作单电子晶体管的岛。此外，源极和漏极由其上沉积有金属的硅或掺杂有杂质的硅形成。因此，岛和隧道壁垒的形成是容易的，批量生产是可能的，并且可以通过氧化来控制岛的尺寸，使得能够容易地制造能够在室温下操作的单电子晶体管。

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