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11. 发明申请

US20080164513A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非挥发性半导体存储器件以及制造非易失性半导体存储器件的方法
公开(公告)号：US20080164513A1
公开(公告)日：2008-07-10
申请号：US11693716
申请日：2007-03-30
申请人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lal , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lal , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.
摘要翻译：本发明涉及一种存储器件及其制造方法。存储器件包括衬底，衬底上的隧道电介质膜，形成在衬底中的源区和漏区对，以及在每对源区和漏区之间的多个分开的存储块。每个存储线块包括存储介质和二氧化硅层。两个存储块以至少100埃的间隔分开。

12. 发明授权

US07218554B2 Method of refreshing charge-trapping non-volatile memory using band-to-band tunneling hot hole (BTBTHH) injection 有权
标题翻译：使用带 - 带隧道热孔（BTBTHH）注入来刷新电荷捕获非易失性存储器的方法
公开(公告)号：US07218554B2
公开(公告)日：2007-05-15
申请号：US11160097
申请日：2005-06-08
申请人： Cheng-Hsing Hsu , Chao-I Wu , Hao-Ming Lien , Ming-Hsiang Hsueh
发明人： Cheng-Hsing Hsu , Chao-I Wu , Hao-Ming Lien , Ming-Hsiang Hsueh
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/0466
摘要： A method of using a non-volatile memory that utilizes a charge-trapping layer for data storage is described. A refresh step is performed, after the non-volatile memory is subject to multiple write/erase cycles causing hard-to-erase electrons in the charge-trapping layer, to eliminate the hard-to-erase electrons. After the refresh step, the non-volatile memory is used again.
摘要翻译：描述了使用利用电荷捕获层进行数据存储的非易失性存储器的方法。在非易失性存储器经受多次写入/擦除周期之后，在电荷俘获层中产生难以擦除的电子的情况下，执行刷新步骤，以消除难以擦除的电子。刷新步骤后，再次使用非易失性存储器。

13. 发明申请

US20070008777A1 NON-VOLATILE MEMORY CELL AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非挥发性记忆细胞及其操作方法
公开(公告)号：US20070008777A1
公开(公告)日：2007-01-11
申请号：US11308777
申请日：2006-05-03
申请人： Ming-Hsiang Hsueh , Ming-Chang Kuo , Min-Ta Wu , Chao-Lun Yu
发明人： Ming-Hsiang Hsueh , Ming-Chang Kuo , Min-Ta Wu , Chao-Lun Yu
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , G11C16/10 , H01L29/42352 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： A non-volatile memory is described. The non-volatile memory includes a first source/drain region, a second source/drain region, a charge-trapping layer and a gate layer. The first source/drain region is disposed beside the top sidewall of a trench in a substrate. The second source/drain region is disposed in the substrate at the bottom of the trench. The gate layer is disposed in the trench and on the substrate. The charge-trapping layer is disposed between the gate layer and the substrate. A plurality of assisted charges is stored in one of the sides of the charge-trapping layer.
摘要翻译：描述非易失性存储器。非易失性存储器包括第一源极/漏极区域，第二源极/漏极区域，电荷俘获层和栅极层。第一源极/漏极区域设置在衬底中的沟槽的顶侧壁旁边。第二源极/漏极区域设置在沟槽底部的衬底中。栅极层设置在沟槽和衬底上。电荷捕获层设置在栅极层和衬底之间。多个辅助电荷存储在电荷捕获层的一侧中。

14. 发明申请

US20080290397A1 MEMORY CELL AND METHOD FOR MANUFACTURING AND OPERATING THE SAME 有权
标题翻译：存储单元及其制造和操作的方法
公开(公告)号：US20080290397A1
公开(公告)日：2008-11-27
申请号：US11753850
申请日：2007-05-25
申请人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L29/42352 , H01L29/66833 , H01L29/792
摘要： A memory cell is disposed on a substrate having plurality of isolation structures that define at least a fin structure in the substrate, wherein the surface of the fin structure is higher than that of the isolation structures. The memory cell includes a gate, a charge trapping structure, a protection layer and two source/drain regions. The gate is disposed on the substrate,and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The protection layer is disposed between the upper portion of the fin structure and the gate separating the charge trapping structure. The source/drain regions are disposed in the fin structure at both sides of the gate.
摘要翻译：存储单元设置在具有多个隔离结构的衬底上，所述隔离结构在衬底中至少限定翅片结构，其中鳍结构的表面高于隔离结构的表面。存储单元包括栅极，电荷俘获结构，保护层和两个源极/漏极区域。栅极设置在基板上，并跨接在翅片结构上。电荷捕获结构设置在栅极和鳍结构之间。保护层设置在翅片结构的上部和分离电荷捕获结构的栅极之间。源极/漏极区域设置在栅极两侧的鳍结构中。

15. 发明申请

US20080137407A1 Memory structure and operating method thereof 有权
标题翻译：存储器结构及其操作方法
公开(公告)号：US20080137407A1
公开(公告)日：2008-06-12
申请号：US11637155
申请日：2006-12-12
申请人： Chao-I Wu , Ming-Hsiang Hsueh
发明人： Chao-I Wu , Ming-Hsiang Hsueh
IPC分类号： G11C11/34 , H01L29/76
CPC分类号： G11C16/10
摘要： A method for operating memory used for enabling the memory device to have a first threshold voltage or a second threshold voltage is provided. The method includes the following procedures. First, an operating voltage is applied to a gate of the memory device for a first time period, such that the memory device has the first threshold voltage. Next, the same operating voltage is applied to the gate of the memory for a second time period, such that the memory device has a second threshold voltage. The duration of the first time period is different from the duration of the second time period.
摘要翻译：提供了一种用于操作用于使存储器件具有第一阈值电压或第二阈值电压的存储器的方法。该方法包括以下步骤。首先，将操作电压施加到存储器件的栅极第一时间段，使得存储器件具有第一阈值电压。接下来，将相同的工作电压施加到存储器的栅极第二时间段，使得存储器件具有第二阈值电压。第一时间段的持续时间与第二时间段的持续时间不同。

16. 发明授权

US07381982B2 Method for fabricating chalcogenide-applied memory 有权
标题翻译：制备硫族化物应用记忆的方法
公开(公告)号：US07381982B2
公开(公告)日：2008-06-03
申请号：US11213533
申请日：2005-08-26
申请人： Ming-Hsiang Hsueh
发明人： Ming-Hsiang Hsueh
IPC分类号： H01L47/00
CPC分类号： H01L45/1273 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/1666 , H01L45/1683 , Y10S438/90
摘要： A chalcogenide memory cell includes a lower electrode, a chalcogenide layer, and an upper electrode. The lower electrode includes a tapered cavity. The chalcogenide layer is formed in the tapered cavity of the lower electrode. One side of the chalcogenide layer is adjacent to the lower electrode. The upper electrode is formed in a second cavity formed by the chalcogenide layer so that the upper electrode substantially fills the second cavity. The upper electrode is adjacent to the other side of the chalcogenide layer. Information is stored and retrieved by passing current between the upper electrode and the lower electrode. The tapered cavity of the lower electrode is formed through anisotropic etching or through sidewall-application. Undesired currents are prevented using an additional dielectric layer or by using an additional conductive layer that forms a p-n junction with the lower electrode.
摘要翻译：硫族化物存储单元包括下电极，硫族化物层和上电极。下电极包括锥形腔。硫族化物层形成在下电极的锥形空腔中。硫属化物层的一侧与下电极相邻。上电极形成在由硫族化物层形成的第二空腔中，使得上电极基本上填充第二腔。上电极与硫族化物层的另一侧相邻。通过在上部电极和下部电极之间传递电流来存储和检索信息。下电极的锥形腔通过各向异性蚀刻或通过侧壁施加形成。使用额外的电介质层或通过使用与下电极形成p-n结的附加导电层来防止不期望的电流。

17. 发明授权

US07932507B2 Current constricting phase change memory element structure 有权
标题翻译：电流限制相变存储元件结构
公开(公告)号：US07932507B2
公开(公告)日：2011-04-26
申请号：US12727672
申请日：2010-03-19
申请人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
发明人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
IPC分类号： H01L29/02
CPC分类号： B82Y10/00 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
摘要翻译：使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝缘体层形成电流收缩层的硬掩模。纳米颗粒优选在下面的表面上自对准和/或自平坦化。电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电材料。电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

18. 发明授权

US07593262B2 Memory structure and operating method thereof 有权
标题翻译：存储器结构及其操作方法
公开(公告)号：US07593262B2
公开(公告)日：2009-09-22
申请号：US11637155
申请日：2006-12-12
申请人： Chao-I Wu , Ming-Hsiang Hsueh
发明人： Chao-I Wu , Ming-Hsiang Hsueh
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A method for operating memory used for enabling the memory device to have a first threshold voltage or a second threshold voltage is provided. The method includes the following procedures. First, an operating voltage is applied to a gate of the memory device for a first time period, such that the memory device has the first threshold voltage. Next, the same operating voltage is applied to the gate of the memory for a second time period, such that the memory device has a second threshold voltage. The duration of the first time period is different from the duration of the second time period.
摘要翻译：提供了一种用于操作用于使存储器件具有第一阈值电压或第二阈值电压的存储器的方法。该方法包括以下步骤。首先，将操作电压施加到存储器件的栅极第一时间段，使得存储器件具有第一阈值电压。接下来，将相同的工作电压施加到存储器的栅极第二时间段，使得存储器件具有第二阈值电压。第一时间段的持续时间与第二时间段的持续时间不同。

19. 发明申请

US20080165569A1 Resistance Limited Phase Change Memory Material 审中-公开
标题翻译：电阻有限相变记忆材料
公开(公告)号：US20080165569A1
公开(公告)日：2008-07-10
申请号：US11619625
申请日：2007-01-04
申请人： Chieh-Fang Chen , Shih-Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
发明人： Chieh-Fang Chen , Shih-Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
IPC分类号： G11C11/00 , H01L21/06 , H01L21/00
CPC分类号： G11C11/5678 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： A memory cell comprises a first electrode, a second electrode and a composite material. The composite material electrically couples the first electrode to the second electrode. Moreover, the composite material comprises a phase change material and a resistor material. At least a portion of the phase change material is operative to switch between a substantially crystalline phase and a substantially amorphous phase in response to an application of a switching signal to at least one of the first and second electrodes. In addition, the resistor material has a resistivity lower than that of the phase change material when the phase change material is in the substantially amorphous phase.
摘要翻译：存储单元包括第一电极，第二电极和复合材料。复合材料将第一电极电耦合到第二电极。此外，复合材料包括相变材料和电阻材料。响应于向第一和第二电极中的至少一个施加开关信号，相变材料的至少一部分可操作以在基本上结晶相和基本非晶相之间切换。此外，当相变材料处于基本非晶相时，电阻材料的电阻率低于相变材料的电阻率。

20. 发明申请

US20080057651A1 METHOD OF MANUFACTURING NON-VOLATILE MEMORY 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US20080057651A1
公开(公告)日：2008-03-06
申请号：US11468575
申请日：2006-08-30
申请人： Ming-Hsiang Hsueh
发明人： Ming-Hsiang Hsueh
IPC分类号： H01L21/8234
CPC分类号： H01L27/105 , H01L27/11521
摘要： A method of manufacturing a non-volatile memory including the following steps is provided. First, a dielectric layer, a first conductive layer and a patterned mask layer are sequentially formed on a substrate. A portion of the first conductive layer is removed using the patterned mask layer as a mask to form a plurality of first gates. An oxidation process is performed to form an oxide layer on the sidewalls of the first gates. The patterned mask layer is removed. A plurality of second gates is formed between two adjacent first gates so that the first gates and the second gates co-exist to form a memory cell column. A doped region is formed in the substrate adjacent to the memory cell column.
摘要翻译：提供一种制造包括以下步骤的非易失性存储器的方法。首先，在基板上依次形成电介质层，第一导电层和图案化掩模层。使用图案化掩模层作为掩模去除第一导电层的一部分以形成多个第一栅极。执行氧化处理以在第一栅极的侧壁上形成氧化物层。去除图案化的掩模层。在两个相邻的第一栅极之间形成多个第二栅极，使得第一栅极和第二栅极共存以形成存储单元列。在与存储单元列相邻的衬底中形成掺杂区域。

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