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1. 发明授权

US07785963B2 Method for fabricating inverted T-shaped floating gate memory 有权
标题翻译：倒T形浮栅存储器的制造方法
公开(公告)号：US07785963B2
公开(公告)日：2010-08-31
申请号：US12036196
申请日：2008-02-22
申请人： Ming-Hsiang Hsueh , Yen-Hao Shih , Erh-Kun Lai
发明人： Ming-Hsiang Hsueh , Yen-Hao Shih , Erh-Kun Lai
IPC分类号： H01L21/8239
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment.
摘要翻译：公开了具有非矩形横截面的浮动栅极的存储器件。非矩形横截面可以是倒T形，梯形或双倒T形。公开了用于制造由于浮动栅极的增加的表面积而具有改进的耦合比的浮动栅极存储器件的方法。存储器件具有浮动栅极，其具有诸如倒T形的横截面形状，使得顶部轮廓不是平坦的线段。

2. 发明授权

US07745807B2 Current constricting phase change memory element structure 失效
标题翻译：电流限制相变存储元件结构
公开(公告)号：US07745807B2
公开(公告)日：2010-06-29
申请号：US11776301
申请日：2007-07-11
申请人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
发明人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
IPC分类号： H01L29/02
CPC分类号： B82Y10/00 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
摘要翻译：使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝缘体层形成电流收缩层的硬掩模。纳米颗粒优选在下面的表面上自对准和/或自平坦化。电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电材料。电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

3. 发明申请

US20090130835A1 METHOD OF MANUFACTURING INVERTED T-SHAPED FLOATING GATE MEMORY 审中-公开
标题翻译：制造反转T型浮动闸门存储器的方法
公开(公告)号：US20090130835A1
公开(公告)日：2009-05-21
申请号：US11941813
申请日：2007-11-16
申请人： Erh-Kun LAI , Yen-Hao SHIH , Ming-Hsiang HSUEH
发明人： Erh-Kun LAI , Yen-Hao SHIH , Ming-Hsiang HSUEH
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L27/11521 , H01L29/40114 , H01L29/42324
摘要： A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T-shape, a U-shape, a trapezoid shape, or a double inverted T-shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T-shape, such that a top contour is a non-flat segment.
摘要翻译：公开了具有非矩形横截面的浮动栅极的存储器件。非矩形横截面可以是倒T形，U形，梯形或双倒T形。公开了用于制造由于浮动栅极的增加的表面积而具有改进的耦合比的浮动栅极存储器件的方法。存储器件具有浮动栅极，其具有诸如倒T形的横截面形状，使得顶部轮廓是非平坦段。

4. 发明申请

US20090014704A1 CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE 失效
标题翻译：当前的相位变化记忆元素结构
公开(公告)号：US20090014704A1
公开(公告)日：2009-01-15
申请号：US11776301
申请日：2007-07-11
申请人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
发明人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
IPC分类号： H01L29/04
CPC分类号： B82Y10/00 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
摘要翻译：使用具有大约10nm的尺寸的纳米颗粒层来形成电流收缩层或用作从底层绝缘体层形成电流收缩层的硬掩模。纳米颗粒优选在下面的表面上自对准和/或自平坦化。电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电材料。电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

5. 发明授权

US07160794B1 Method of fabricating non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US07160794B1
公开(公告)日：2007-01-09
申请号：US11162042
申请日：2005-08-26
申请人： Ming-Hsiang Hsueh , Shih-Chang Tsai
发明人： Ming-Hsiang Hsueh , Shih-Chang Tsai
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11521 , Y10S438/926
摘要： A method for manufacturing a non-volatile memory. The method comprises steps of forming a first dielectric layer on a substrate and forming a dummy gate layer on the first dielectric layer. Further, the dummy gate layer is defined to form a plurality of dummy gates and a doped region is formed in the substrate by using the dummy gates as a mask. A second dielectric layer is formed on a portion of the first dielectric layer corresponding to the location of the doped region and the dummy gates are removed to expose a portion of the first dielectric layer. A conductive layer is formed over the substrate to cover the second dielectric layer and the first dielectric layer.
摘要翻译：一种用于制造非易失性存储器的方法。该方法包括以下步骤：在衬底上形成第一电介质层，并在第一电介质层上形成虚拟栅极层。此外，将虚拟栅极层限定为形成多个伪栅极，并且通过使用伪栅极作为掩模在衬底中形成掺杂区域。在第一介电层的与掺杂区域的位置对应的部分上形成第二电介质层，并且去除伪栅极以暴露第一介电层的一部分。导电层形成在衬底上以覆盖第二电介质层和第一电介质层。

6. 发明授权

US06972429B1 Chalcogenide random access memory and method of fabricating the same 有权
标题翻译：硫族元素随机存取存储器及其制造方法
公开(公告)号：US06972429B1
公开(公告)日：2005-12-06
申请号：US10905115
申请日：2004-12-16
申请人： Ming-Hsiang Hsueh , Shih-Hong Chen
发明人： Ming-Hsiang Hsueh , Shih-Hong Chen
IPC分类号： H01L29/04 , H01L45/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/165
摘要： A method of fabricating a chalcogenide random access memory (CRAM) is provided. The method is to provide a substrate having a bottom electrode thereon and then form a chalcogenide film and a patterned mask corresponding to the bottom electrode sequentially over the substrate. Thereafter, using the patterned mask, an ion implantation is performed to convert a portion of the chalcogenide film into a modified region while the chalcogenide film underneath the patterned mask is prevented from receiving any dopants and hence is kept as a non-modified region. The modified region has a lower conductivity than the non-modified region. After that, the patterned mask is removed and then a top electrode is formed over the non-modified region. Utilizing the ion implantation as a modifying treatment, the contact area between the chalcogenide film and the bottom electrode is decreased and the operating current of the CRAM is reduced.
摘要翻译：提供了制造硫族化物随机存取存储器（CRAM）的方法。该方法是提供其上具有底部电极的衬底，然后在衬底上依次形成对应于底部电极的硫族化物膜和图案化掩模。此后，使用图案化掩模，执行离子注入以将硫族化物膜的一部分转化为改性区域，同时防止图案化掩模下方的硫族化物膜接收任何掺杂剂，因此保持为未改性区域。改性区域的导电率低于非改性区域。之后，去除图案化掩模，然后在非改性区域上形成顶部电极。利用离子注入作为改性处理，硫族化物膜与底部电极之间的接触面积减小，并且CRAM的工作电流降低。

7. 发明授权

US07795088B2 Method for manufacturing memory cell 有权
标题翻译：制造存储单元的方法
公开(公告)号：US07795088B2
公开(公告)日：2010-09-14
申请号：US11753850
申请日：2007-05-25
申请人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/28282 , H01L29/42352 , H01L29/66833 , H01L29/792
摘要： A method for manufacturing memory cells is provided. First, a substrate is provided, wherein a liner layer and a material layer have already been sequentially formed on the substrate. Thereafter, a patterned mask layer is formed on the substrate. Then, the patterned mask layer is trimmed. Subsequently, a portion of the material layer, a portion of the liner layer and a portion of the substrate are removed by using the patterned mask layer as a mask to define a plurality of fin-structures in the substrate. Afterward, the patterned mask layer is removed and a plurality of isolation structures among the fin structures is formed. The surface of the isolation structures is lower than that of the fin structures. Following that, charge trapping structures are formed on the substrate, covering the fin structures. Succeeding, a portion of the charge trapping structures is removed to expose the material layer. Then, the treatment process turns the material layer into a protection layer. Subsequently, a gate is formed on the substrate and straddles the protection layer, the charge trapping structures and the fin structure. Afterward, source/drain regions are formed in the fin-structure exposed by both sides of the gate.
摘要翻译：提供一种用于制造存储器单元的方法。首先，提供衬底，其中衬底层和材料层已经顺序形成在衬底上。此后，在衬底上形成图案化掩模层。然后，修整图案化的掩模层。随后，通过使用图案化掩模层作为掩模来去除材料层的一部分，衬垫层的一部分和衬底的一部分，以在衬底中限定多个鳍结构。之后，去除图案化的掩模层，并且形成翅片结构中的多个隔离结构。隔离结构的表面比翅片结构的表面低。之后，在基片上形成电荷俘获结构，覆盖翅片结构。成功地，去除一部分电荷捕获结构以暴露材料层。然后，处理过程将材料层转变成保护层。随后，在基板上形成栅极，跨越保护层，电荷捕获结构和鳍结构。之后，源极/漏极区域形成在由栅极两侧暴露的鳍状结构中。

8. 发明授权

US07772068B2 Method of manufacturing non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US07772068B2
公开(公告)日：2010-08-10
申请号：US11468575
申请日：2006-08-30
申请人： Ming-Hsiang Hsueh
发明人： Ming-Hsiang Hsueh
IPC分类号： H01L21/8247
CPC分类号： H01L27/105 , H01L27/11521
摘要： A method of manufacturing a non-volatile memory including the following steps is provided. First, a dielectric layer, a first conductive layer and a patterned mask layer are sequentially formed on a substrate. A portion of the first conductive layer is removed using the patterned mask layer as a mask to form a plurality of first gates. An oxidation process is performed to form an oxide layer on the sidewalls of the first gates. The patterned mask layer is removed. A plurality of second gates is formed between two adjacent first gates so that the first gates and the second gates co-exist to form a memory cell column. A doped region is formed in the substrate adjacent to the memory cell column.
摘要翻译：提供一种制造包括以下步骤的非易失性存储器的方法。首先，在基板上依次形成电介质层，第一导电层和图案化掩模层。使用图案化掩模层作为掩模去除第一导电层的一部分以形成多个第一栅极。执行氧化处理以在第一栅极的侧壁上形成氧化物层。去除图案化的掩模层。在两个相邻的第一栅极之间形成多个第二栅极，使得第一栅极和第二栅极共存以形成存储单元列。在与存储单元列相邻的衬底中形成掺杂区域。

9. 发明申请

US20090215256A1 Inverted T-Shaped Floating Gate Memory and Method for Fabricating the Same 有权
标题翻译：反相T形浮动门存储器及其制造方法
公开(公告)号：US20090215256A1
公开(公告)日：2009-08-27
申请号：US12036196
申请日：2008-02-22
申请人： Ming-Hsiang HSUEH , Yen-Hao SHIH , Erh-Kun LAI
发明人： Ming-Hsiang HSUEH , Yen-Hao SHIH , Erh-Kun LAI
IPC分类号： H01L21/3205
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment.
摘要翻译：公开了具有非矩形横截面的浮动栅极的存储器件。非矩形横截面可以是倒T形，梯形或双倒T形。公开了用于制造由于浮动栅极的增加的表面积而具有改进的耦合比的浮动栅极存储器件的方法。存储器件具有浮动栅极，其具有诸如倒T形的横截面形状，使得顶部轮廓不是平坦的线段。

10. 发明授权

US07521321B2 Method of fabricating a non-volatile semiconductor memory device 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US07521321B2
公开(公告)日：2009-04-21
申请号：US11693716
申请日：2007-03-30
申请人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lai , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lai , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.
摘要翻译：本发明涉及一种存储器件及其制造方法。存储器件包括衬底，衬底上的隧道电介质膜，形成在衬底中的源区和漏区对，以及在每对源区和漏区之间的多个分开的存储块。每个存储线块包括存储介质和二氧化硅层。两个存储块以至少100埃的间隔分开。

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