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1. 发明申请

US20070008777A1 NON-VOLATILE MEMORY CELL AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非挥发性记忆细胞及其操作方法
公开(公告)号：US20070008777A1
公开(公告)日：2007-01-11
申请号：US11308777
申请日：2006-05-03
申请人： Ming-Hsiang Hsueh , Ming-Chang Kuo , Min-Ta Wu , Chao-Lun Yu
发明人： Ming-Hsiang Hsueh , Ming-Chang Kuo , Min-Ta Wu , Chao-Lun Yu
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , G11C16/10 , H01L29/42352 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： A non-volatile memory is described. The non-volatile memory includes a first source/drain region, a second source/drain region, a charge-trapping layer and a gate layer. The first source/drain region is disposed beside the top sidewall of a trench in a substrate. The second source/drain region is disposed in the substrate at the bottom of the trench. The gate layer is disposed in the trench and on the substrate. The charge-trapping layer is disposed between the gate layer and the substrate. A plurality of assisted charges is stored in one of the sides of the charge-trapping layer.
摘要翻译：描述非易失性存储器。非易失性存储器包括第一源极/漏极区域，第二源极/漏极区域，电荷俘获层和栅极层。第一源极/漏极区域设置在衬底中的沟槽的顶侧壁旁边。第二源极/漏极区域设置在沟槽底部的衬底中。栅极层设置在沟槽和衬底上。电荷捕获层设置在栅极层和衬底之间。多个辅助电荷存储在电荷捕获层的一侧中。

2. 发明授权

US08304755B2 Three-dimensional semiconductor structure 有权
标题翻译：三维半导体结构
公开(公告)号：US08304755B2
公开(公告)日：2012-11-06
申请号：US12372860
申请日：2009-02-18
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： H01L47/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： A three-dimensional (3D) semiconductor structure with high density and method of fabricating the same are disclosed. The 3D semiconductor structure comprises at least a first memory cell and a second memory cell stacked on the first memory cell. The first memory cell comprises a first conductive line and a second conductive line. The second memory cell comprises another first conductive line opposite to the first conductive line of the first memory cell, and the second conductive line formed between said two first conductive lines of the first and second memory cells. The first and second memory cells share the second conductive line when the 3D semiconductor structure is programming and erasing, and each of the first and second memory cells has a diode.
摘要翻译：公开了一种具有高密度的三维（3D）半导体结构及其制造方法。 3D半导体结构包括至少第一存储单元和堆叠在第一存储单元上的第二存储单元。第一存储单元包括第一导线和第二导线。第二存储单元包括与第一存储单元的第一导线相对的另一第一导线，以及形成在第一和第二存储单元的所述两个第一导线之间的第二导线。当3D半导体结构编程和擦除时，第一和第二存储单元共享第二导线，并且第一和第二存储单元中的每一个具有二极管。

3. 发明授权

US07936607B2 Non-volatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07936607B2
公开(公告)日：2011-05-03
申请号：US12465872
申请日：2009-05-14
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3404
摘要： A non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each cell including a portion of the substrate, a control gate, a charge-storing layer between the portion of the substrate and the control gate, and two S/D regions of a second conductivity type in the portion of the substrate. A circuit provides a first voltage to the substrate and a second voltage to both S/D regions of each cell, wherein the difference between the first and second voltages is sufficient to cause band-to-band tunneling hot holes. The circuit also provides a voltage to the control gate and the period of applying the voltages are controlled such that the threshold voltages of all the cells converge in a tolerable range.
摘要翻译：非挥发性存储器包括在第一导电类型的衬底上的多个单元，每个单元包括衬底的一部分，控制栅极，在衬底的部分和控制栅极之间的电荷存储层，以及两个第二导电类型的S / D区域在衬底的该部分中。电路向基板提供第一电压，并向每个单元的两个S / D区域提供第二电压，其中第一和第二电压之间的差值足以引起带对隧道的热孔。电路还向控制栅极提供电压，并且控制施加电压的周期使得所有单元的阈值电压在可容许的范围内收敛。

4. 发明申请

US20110013462A1 Method for Operating Memory 有权
标题翻译：操作内存的方法
公开(公告)号：US20110013462A1
公开(公告)日：2011-01-20
申请号：US12889710
申请日：2010-09-24
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C11/5621 , G11C16/0416
摘要： A memory operating method includes the following steps. First, a memory with a charge storage structure is provided. Next, the memory is biased to a first threshold voltage. Then, the memory is biased to a second threshold voltage. Next, the memory is biased to a third threshold voltage. The first threshold voltage is higher than a first level. The second threshold voltage is lower than a second level. The third threshold voltage is approximating or equal to the second level.
摘要翻译：存储器操作方法包括以下步骤。首先，提供具有电荷存储结构的存储器。接下来，存储器被偏置到第一阈值电压。然后，存储器被偏置到第二阈值电压。接下来，存储器被偏置到第三阈值电压。第一阈值电压高于第一电平。第二阈值电压低于第二电平。第三阈值电压接近或等于第二电平。

5. 发明授权

US07778081B2 Method for performing operations by applying periodic voltage pulses to control gate of an ono memory cell 有权
标题翻译：通过施加周期性电压脉冲来控制存储单元的栅极来执行操作的方法
公开(公告)号：US07778081B2
公开(公告)日：2010-08-17
申请号：US11945181
申请日：2007-11-26
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0466 , G11C16/3468 , G11C16/3477 , G11C16/3486
摘要： A method for performing operations on a memory cell is described. The memory cell includes a substrate, a first doping region and a second doping region. The first doping region and the second doping region are formed on the substrate with a channel region therebetween. A dielectric layer is formed above the channel region and a conductive gate is formed over the dielectric layer. The method includes applying a first constant voltage for a first period to the conductive gate followed by applying a second constant voltage for a second period to the conductive gate repeatedly. The value of the first constant voltage is different from the value of the second constant voltage. A third constant voltage and a fourth voltage are applied to the first doping region and the second doping region respectively.
摘要翻译：描述了对存储器单元执行操作的方法。存储单元包括衬底，第一掺杂区和第二掺杂区。第一掺杂区域和第二掺杂区域形成在衬底上，其间具有沟道区域。介电层形成在沟道区上方，导电栅极形成在电介质层的上方。该方法包括将第一周期的第一恒定电压施加到导电栅极，然后将第二周期的第二恒定电压重复施加到导电栅极。第一恒定电压的值与第二恒定电压的值不同。第三恒定电压和第四电压分别施加到第一掺杂区域和第二掺杂区域。

6. 发明授权

US07655970B2 Single poly non-volatile memory device with inversion diffusion regions and methods for operating the same 有权
标题翻译：具有反向扩散区域的单多晶非易失性存储器件及其操作方法
公开(公告)号：US07655970B2
公开(公告)日：2010-02-02
申请号：US11359028
申请日：2006-02-22
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： H01L29/94
CPC分类号： H01L29/7883 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/66825
摘要： A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed next to each other on top of the dielectric layer separated by a gap. Accordingly, a non-volatile memory device can be constructed using a single poly process that is compatible with conventional CMOS processes. In addition, assist gates are formed on the dielectric layer next to the control gate and floating gate respectively.
摘要翻译：非易失性存储器件包括其上形成有电介质层的衬底。然后在由间隙分开的电介质层的顶部上彼此相邻地形成控制栅极和浮置栅极。因此，可以使用与常规CMOS工艺兼容的单一多工艺来构造非易失性存储器件。另外，分别在控制栅极和浮动栅极旁边的电介质层上形成辅助栅极。

7. 发明申请

US20090185428A1 OPERATING METHOD OF MULTI-LEVEL MEMORY CELL 有权
标题翻译：多级记忆体的操作方法
公开(公告)号：US20090185428A1
公开(公告)日：2009-07-23
申请号：US12017573
申请日：2008-01-22
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C16/3468 , G11C11/5628 , G11C11/5635 , G11C16/0466 , G11C2211/5621 , G11C2211/5648
摘要： An operating method of a memory cell is described, wherein the memory cell has a plurality of threshold voltages. The operating method includes programming the cell from an initial state to a programmed state. The initial state is an erased state having a threshold voltage between the lowest threshold voltage and the highest one among the plurality of threshold voltages.
摘要翻译：描述存储单元的操作方法，其中存储单元具有多个阈值电压。操作方法包括将单元从初始状态编程到编程状态。初始状态是具有阈值电压在多个阈值电压中的最低阈值电压和最高阈值电压之间的擦除状态。

8. 发明授权

US07554851B2 Reset method of non-volatile memory 有权
标题翻译：非易失性存储器的复位方法
公开(公告)号：US07554851B2
公开(公告)日：2009-06-30
申请号：US11620450
申请日：2007-01-05
申请人： Ming-Chang Kuo
发明人： Ming-Chang Kuo
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3404
摘要： A reset method of a non-volatile memory is described. The non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each including a portion of the substrate, a control gate, a charge-storing layer between the portion of the substrate and the control gate, and two S/D regions of a second conductivity type in the portion of the substrate. The reset method utilizes a DSB-BTBTHH effect. A first voltage is applied to the substrate and a second voltage to both S/D regions of each cell, wherein the difference between the first and second voltages is sufficient to cause band-to-band tunneling hot holes. A voltage applied to the control gate and the period of applying the voltages are controlled such that the threshold voltages of all the cells converge in a tolerable range.
摘要翻译：描述非易失性存储器的复位方法。非易失性存储器包括在第一导电类型的衬底上的多个单元，每个单元包括衬底的一部分，控制栅极，在衬底的部分和控制栅极之间的电荷存储层，以及两个S / D区域的第二导电类型。复位方法使用DSB-BTBTHH效果。向基板施加第一电压，对每个单元的两个S / D区域施加第二电压，其中第一和第二电压之间的差异足以引起带对隧道的热孔。控制施加到控制栅极的电压和施加电压的周期，使得所有单元的阈值电压在可容许的范围内收敛。

9. 发明授权

US07474562B2 Method of forming and operating an assisted charge memory device 有权
标题翻译：形成和操作辅助电荷存储器件的方法
公开(公告)号：US07474562B2
公开(公告)日：2009-01-06
申请号：US11292024
申请日：2005-12-01
申请人： Ming-Chang Kuo , Chao-I Wu , Ming-Hsin Lee , Tzu-Hsuan Hsu
发明人： Ming-Chang Kuo , Chao-I Wu , Ming-Hsin Lee , Tzu-Hsuan Hsu
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , H01L21/28282 , H01L29/42332 , H01L29/7887 , H01L29/7923
摘要： A method is provided of forming an assisted charge memory (AC-memory) cell. The method uses a two-sided charge trap memory cell that includes a two-sided charge trapping layer. A charge is formed in at least a portion of the two-sided charge trapping layer. One side (AC-side) of the two-sided charge trapping layer always has a fixed high threshold voltage (Vt) level which is the assisted charge for the AC-memory cell. The other side (data-side) is used for memory operations.
摘要翻译：提供了形成辅助电荷存储器（AC-存储器）单元的方法。该方法使用包括双面电荷捕获层的双面电荷陷阱存储单元。在双面电荷俘获层的至少一部分中形成电荷。双面电荷捕获层的一侧（AC侧）总是具有固定的高阈值电压（Vt）电平，其为AC存储单元的辅助电荷。另一方（数据端）用于存储器操作。

10. 发明申请

US20070267677A1 SINGLE POLY NON-VOLATILE MEMORY DEVICE WITH INVERSION DIFFUSION REGIONS AND METHODS FOR OPERATING THE SAME 有权
标题翻译：具有反向扩散区域的单个聚合非挥发性存储器件及其操作方法
公开(公告)号：US20070267677A1
公开(公告)日：2007-11-22
申请号：US11383924
申请日：2006-05-17
申请人： Ming-Chang Kuo , Chao-I Wu
发明人： Ming-Chang Kuo , Chao-I Wu
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , G11C16/0433 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/66825
摘要： A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed on top of the dielectric layer. Accordingly, a non-volatile memory device can be constructed using a single poly process that is compatible with conventional CMOS processes. In addition, an assist gate, or assist gates are formed on the dielectric layer next to and between the control gate and floating gate respectively. The assist gates are used to form inversion diffusion regions in the substrate. By using the assist gates to form inversion diffusion regions, the overall size of the device can be reduced, which can improve device density.
摘要翻译：非易失性存储器件包括其上形成有电介质层的衬底。然后在电介质层的顶部形成控制栅极和浮置栅极。因此，可以使用与常规CMOS工艺兼容的单一多工艺来构造非易失性存储器件。此外，辅助栅极或辅助栅极分别形成在控制栅极和浮置栅极之间和之间的电介质层上。辅助栅极用于在衬底中形成反向扩散区域。通过使用辅助栅极形成反向扩散区域，可以减小器件的整体尺寸，这可以提高器件密度。

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