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1. 发明申请

US20100193763A1 CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE 有权
标题翻译：当前的相位变化记忆元素结构
公开(公告)号：US20100193763A1
公开(公告)日：2010-08-05
申请号：US12727672
申请日：2010-03-19
申请人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
发明人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
IPC分类号： H01L45/00
CPC分类号： B82Y10/00 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
摘要翻译：使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝缘体层形成电流收缩层的硬掩模。纳米颗粒优选在下面的表面上自对准和/或自平坦化。电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电材料。电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

2. 发明授权

US07932507B2 Current constricting phase change memory element structure 有权
标题翻译：电流限制相变存储元件结构
公开(公告)号：US07932507B2
公开(公告)日：2011-04-26
申请号：US12727672
申请日：2010-03-19
申请人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
发明人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
IPC分类号： H01L29/02
CPC分类号： B82Y10/00 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
摘要翻译：使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝缘体层形成电流收缩层的硬掩模。纳米颗粒优选在下面的表面上自对准和/或自平坦化。电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电材料。电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

3. 发明申请

US20080165569A1 Resistance Limited Phase Change Memory Material 审中-公开
标题翻译：电阻有限相变记忆材料
公开(公告)号：US20080165569A1
公开(公告)日：2008-07-10
申请号：US11619625
申请日：2007-01-04
申请人： Chieh-Fang Chen , Shih-Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
发明人： Chieh-Fang Chen , Shih-Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
IPC分类号： G11C11/00 , H01L21/06 , H01L21/00
CPC分类号： G11C11/5678 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： A memory cell comprises a first electrode, a second electrode and a composite material. The composite material electrically couples the first electrode to the second electrode. Moreover, the composite material comprises a phase change material and a resistor material. At least a portion of the phase change material is operative to switch between a substantially crystalline phase and a substantially amorphous phase in response to an application of a switching signal to at least one of the first and second electrodes. In addition, the resistor material has a resistivity lower than that of the phase change material when the phase change material is in the substantially amorphous phase.
摘要翻译：存储单元包括第一电极，第二电极和复合材料。复合材料将第一电极电耦合到第二电极。此外，复合材料包括相变材料和电阻材料。响应于向第一和第二电极中的至少一个施加开关信号，相变材料的至少一部分可操作以在基本上结晶相和基本非晶相之间切换。此外，当相变材料处于基本非晶相时，电阻材料的电阻率低于相变材料的电阻率。

4. 发明授权

US07745807B2 Current constricting phase change memory element structure 失效
标题翻译：电流限制相变存储元件结构
公开(公告)号：US07745807B2
公开(公告)日：2010-06-29
申请号：US11776301
申请日：2007-07-11
申请人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
发明人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
IPC分类号： H01L29/02
CPC分类号： B82Y10/00 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
摘要翻译：使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝缘体层形成电流收缩层的硬掩模。纳米颗粒优选在下面的表面上自对准和/或自平坦化。电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电材料。电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

5. 发明申请

US20090014704A1 CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE 失效
标题翻译：当前的相位变化记忆元素结构
公开(公告)号：US20090014704A1
公开(公告)日：2009-01-15
申请号：US11776301
申请日：2007-07-11
申请人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
发明人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
IPC分类号： H01L29/04
CPC分类号： B82Y10/00 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
摘要翻译：使用具有大约10nm的尺寸的纳米颗粒层来形成电流收缩层或用作从底层绝缘体层形成电流收缩层的硬掩模。纳米颗粒优选在下面的表面上自对准和/或自平坦化。电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电材料。电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

6. 发明申请

US20080290397A1 MEMORY CELL AND METHOD FOR MANUFACTURING AND OPERATING THE SAME 有权
标题翻译：存储单元及其制造和操作的方法
公开(公告)号：US20080290397A1
公开(公告)日：2008-11-27
申请号：US11753850
申请日：2007-05-25
申请人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L29/42352 , H01L29/66833 , H01L29/792
摘要： A memory cell is disposed on a substrate having plurality of isolation structures that define at least a fin structure in the substrate, wherein the surface of the fin structure is higher than that of the isolation structures. The memory cell includes a gate, a charge trapping structure, a protection layer and two source/drain regions. The gate is disposed on the substrate,and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The protection layer is disposed between the upper portion of the fin structure and the gate separating the charge trapping structure. The source/drain regions are disposed in the fin structure at both sides of the gate.
摘要翻译：存储单元设置在具有多个隔离结构的衬底上，所述隔离结构在衬底中至少限定翅片结构，其中鳍结构的表面高于隔离结构的表面。存储单元包括栅极，电荷俘获结构，保护层和两个源极/漏极区域。栅极设置在基板上，并跨接在翅片结构上。电荷捕获结构设置在栅极和鳍结构之间。保护层设置在翅片结构的上部和分离电荷捕获结构的栅极之间。源极/漏极区域设置在栅极两侧的鳍结构中。

7. 发明申请

US20080137407A1 Memory structure and operating method thereof 有权
标题翻译：存储器结构及其操作方法
公开(公告)号：US20080137407A1
公开(公告)日：2008-06-12
申请号：US11637155
申请日：2006-12-12
申请人： Chao-I Wu , Ming-Hsiang Hsueh
发明人： Chao-I Wu , Ming-Hsiang Hsueh
IPC分类号： G11C11/34 , H01L29/76
CPC分类号： G11C16/10
摘要： A method for operating memory used for enabling the memory device to have a first threshold voltage or a second threshold voltage is provided. The method includes the following procedures. First, an operating voltage is applied to a gate of the memory device for a first time period, such that the memory device has the first threshold voltage. Next, the same operating voltage is applied to the gate of the memory for a second time period, such that the memory device has a second threshold voltage. The duration of the first time period is different from the duration of the second time period.
摘要翻译：提供了一种用于操作用于使存储器件具有第一阈值电压或第二阈值电压的存储器的方法。该方法包括以下步骤。首先，将操作电压施加到存储器件的栅极第一时间段，使得存储器件具有第一阈值电压。接下来，将相同的工作电压施加到存储器的栅极第二时间段，使得存储器件具有第二阈值电压。第一时间段的持续时间与第二时间段的持续时间不同。

8. 发明授权

US07381982B2 Method for fabricating chalcogenide-applied memory 有权
标题翻译：制备硫族化物应用记忆的方法
公开(公告)号：US07381982B2
公开(公告)日：2008-06-03
申请号：US11213533
申请日：2005-08-26
申请人： Ming-Hsiang Hsueh
发明人： Ming-Hsiang Hsueh
IPC分类号： H01L47/00
CPC分类号： H01L45/1273 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/1666 , H01L45/1683 , Y10S438/90
摘要： A chalcogenide memory cell includes a lower electrode, a chalcogenide layer, and an upper electrode. The lower electrode includes a tapered cavity. The chalcogenide layer is formed in the tapered cavity of the lower electrode. One side of the chalcogenide layer is adjacent to the lower electrode. The upper electrode is formed in a second cavity formed by the chalcogenide layer so that the upper electrode substantially fills the second cavity. The upper electrode is adjacent to the other side of the chalcogenide layer. Information is stored and retrieved by passing current between the upper electrode and the lower electrode. The tapered cavity of the lower electrode is formed through anisotropic etching or through sidewall-application. Undesired currents are prevented using an additional dielectric layer or by using an additional conductive layer that forms a p-n junction with the lower electrode.
摘要翻译：硫族化物存储单元包括下电极，硫族化物层和上电极。下电极包括锥形腔。硫族化物层形成在下电极的锥形空腔中。硫属化物层的一侧与下电极相邻。上电极形成在由硫族化物层形成的第二空腔中，使得上电极基本上填充第二腔。上电极与硫族化物层的另一侧相邻。通过在上部电极和下部电极之间传递电流来存储和检索信息。下电极的锥形腔通过各向异性蚀刻或通过侧壁施加形成。使用额外的电介质层或通过使用与下电极形成p-n结的附加导电层来防止不期望的电流。

9. 发明授权

US07785963B2 Method for fabricating inverted T-shaped floating gate memory 有权
标题翻译：倒T形浮栅存储器的制造方法
公开(公告)号：US07785963B2
公开(公告)日：2010-08-31
申请号：US12036196
申请日：2008-02-22
申请人： Ming-Hsiang Hsueh , Yen-Hao Shih , Erh-Kun Lai
发明人： Ming-Hsiang Hsueh , Yen-Hao Shih , Erh-Kun Lai
IPC分类号： H01L21/8239
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment.
摘要翻译：公开了具有非矩形横截面的浮动栅极的存储器件。非矩形横截面可以是倒T形，梯形或双倒T形。公开了用于制造由于浮动栅极的增加的表面积而具有改进的耦合比的浮动栅极存储器件的方法。存储器件具有浮动栅极，其具有诸如倒T形的横截面形状，使得顶部轮廓不是平坦的线段。

10. 发明授权

US07160794B1 Method of fabricating non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US07160794B1
公开(公告)日：2007-01-09
申请号：US11162042
申请日：2005-08-26
申请人： Ming-Hsiang Hsueh , Shih-Chang Tsai
发明人： Ming-Hsiang Hsueh , Shih-Chang Tsai
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11521 , Y10S438/926
摘要： A method for manufacturing a non-volatile memory. The method comprises steps of forming a first dielectric layer on a substrate and forming a dummy gate layer on the first dielectric layer. Further, the dummy gate layer is defined to form a plurality of dummy gates and a doped region is formed in the substrate by using the dummy gates as a mask. A second dielectric layer is formed on a portion of the first dielectric layer corresponding to the location of the doped region and the dummy gates are removed to expose a portion of the first dielectric layer. A conductive layer is formed over the substrate to cover the second dielectric layer and the first dielectric layer.
摘要翻译：一种用于制造非易失性存储器的方法。该方法包括以下步骤：在衬底上形成第一电介质层，并在第一电介质层上形成虚拟栅极层。此外，将虚拟栅极层限定为形成多个伪栅极，并且通过使用伪栅极作为掩模在衬底中形成掺杂区域。在第一介电层的与掺杂区域的位置对应的部分上形成第二电介质层，并且去除伪栅极以暴露第一介电层的一部分。导电层形成在衬底上以覆盖第二电介质层和第一电介质层。

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