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11. 发明申请

US20050237806A1 Circuit and method for detecting skew of transistor in semiconductor device 失效
标题翻译：用于检测半导体器件中晶体管的偏斜的电路和方法
公开(公告)号：US20050237806A1
公开(公告)日：2005-10-27
申请号：US11019395
申请日：2004-12-23
申请人： Hwang Hur , Jun-Gi Choi
发明人： Hwang Hur , Jun-Gi Choi
IPC分类号： G11C7/00 , G11C16/04 , G11C29/50
CPC分类号： G11C29/50 , G11C29/12005 , G11C2029/5002
摘要： A circuit and method for easily detecting skew of a transistor within a semiconductor device are provided. The circuit for detecting the skew of the transistor includes a linear voltage generating unit for outputting a linear voltage by using a first supply voltage, a first attenuation unit for reducing variation width of the linear voltage according to the performance of the transistor, a saturation voltage generating unit for outputting a saturation voltage by using a second supply voltage, and a comparison unit for comparing an output of the first attenuation unit and the saturation voltage.
摘要翻译：提供一种用于容易地检测半导体器件内的晶体管的偏斜的电路和方法。用于检测晶体管的偏斜的电路包括用于通过使用第一电源电压输出线性电压的线性电压产生单元，用于根据晶体管的性能减小线性电压的变化幅度的第一衰减单元，饱和电压产生单元，用于通过使用第二电源电压输出饱和电压;以及比较单元，用于比较第一衰减单元的输出和饱和电压。

12. 发明申请

US20050206430A1 Skew detection device 有权
标题翻译：偏斜检测装置
公开(公告)号：US20050206430A1
公开(公告)日：2005-09-22
申请号：US10878444
申请日：2004-06-28
申请人： Jun Gi Choi
发明人： Jun Gi Choi
IPC分类号： G11C8/00 , G01R31/26 , H03L5/00
CPC分类号： G01R31/2621 , G01R31/2628
摘要： The present invention discloses a skew detection device which can detect a skew of a transistor changed due to a driving voltage, a size and a process variable. The skew detection device includes a first potential level generator for outputting a first voltage, a second potential level generator for outputting a second voltage, a first level shifter for receiving the first voltage and outputting a first shift voltage, a second level shifter for receiving the second voltage and outputting a second shift voltage, and a comparator for comparing the first shift voltage with the second shift voltage. The first voltage is determined according to a drain-source current of a first MOS transistor operated in a linear region, and the second voltage is determined according to a drain-source current of a second MOS transistor operated in a saturation region.
摘要翻译：本发明公开了一种可以检测由于驱动电压，尺寸和过程变量而改变的晶体管的偏斜的偏斜检测装置。偏斜检测装置包括用于输出第一电压的第一电位电平发生器，用于输出第二电压的第二电位电平发生器，用于接收第一电压并输出第一移位电压的第一电平移位器，用于接收第一电压的第二电平移位器第二电压并输出第二移位电压;以及比较器，用于将第一移位电压与第二移位电压进行比较。根据在线性区域中工作的第一MOS晶体管的漏 - 源电流来确定第一电压，并且根据在饱和区域中操作的第二MOS晶体管的漏 - 源电流来确定第二电压。

13. 发明授权

US06751134B2 Internal voltage generating apparatus for a semiconductor memory device 有权
标题翻译：一种用于半导体存储器件的内部电压产生装置
公开(公告)号：US06751134B2
公开(公告)日：2004-06-15
申请号：US10330887
申请日：2002-12-27
申请人： Jun Gi Choi , Tae Yun Kim
发明人： Jun Gi Choi , Tae Yun Kim
IPC分类号： G11C700
CPC分类号： G11C29/12005 , G11C11/401 , G11C11/4074 , G11C29/12 , G11C2207/105
摘要： An internal voltage generating apparatus for a semiconductor memory device is described herein. The internal voltage generating apparatus is configured to execute an internal voltage margin test with a small number of pads by installing a forcing pad and fuse (or switch) in an initial reference voltage generating terminal during a multi-chip product test of the DRAM to cut down expenses, and to overcome load or noise due to the forcing pad by cutting (switching off) the fuse after a wafer level test during a normal operation.
摘要翻译：本文描述了一种用于半导体存储器件的内部电压产生装置。内部电压发生装置被配置为通过在DRAM的多芯片产品测试期间将迫击焊盘和熔丝（或开关）安装在初始参考电压产生端子中来执行具有少量焊盘的内部电压裕度测试并且在正常操作期间通过在晶圆级测试之后切断（断开）熔断器来克服由于强迫焊盘引起的负载或噪声。

14. 发明授权

US06333249B2 Method for fabricating a semiconductor device 失效
公开(公告)号：US06333249B2
公开(公告)日：2001-12-25
申请号：US09751941
申请日：2001-01-02
申请人： Seon Soon Kim , Jun Gi Choi
发明人： Seon Soon Kim , Jun Gi Choi
IPC分类号： H01L213205
CPC分类号： H01L27/10894 , H01L21/823842 , H01L27/10873
摘要： A method for fabricating a semiconductor device is disclosed. In a process for fabricating a CMOS transistor of a high integrated semiconductor device and a cell of a DRAM, a process for forming a dual gate electrode having a layered structure of a tungsten layer and a polysilicon layer includes the steps of forming a gate electrode shape from an undoped polysilicon layer, forming an insulating film spacer at sidewalls of the polysilicon layer, forming an LDD region, removing a portion of the undoped polysilicon layer to leave a predetermined thickness and to form an opening in which the tungsten layer will be formed, and respectively implanting different impurity ions into the undoped polysilicon layer respectively formed in the PMOS region and the NMOS region before forming the tungsten layer. Thus, it is possible to prevent etching residue from occurring and also prevent the semiconductor substrate from being damaged. In addition, it is possible to prevent the tungsten layer from being oxidized due to a high temperature process such as an ion plantation process for forming the LDD region and the source/drain region, thereby improving operational characteristics of the device and process yield.

15. 发明授权

US08350362B2 Semiconductor integrated circuit and method for fabricating the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US08350362B2
公开(公告)日：2013-01-08
申请号：US12831341
申请日：2010-07-07
申请人： Sang-Jin Byeon , Jun-Gi Choi
发明人： Sang-Jin Byeon , Jun-Gi Choi
IPC分类号： H01L29/40
CPC分类号： H01L21/76879 , H01L23/481 , H01L23/5256 , H01L25/0657 , H01L2225/06527 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.
摘要翻译：半导体集成电路包括：半导体芯片; 通过芯片穿过设置在半导体芯片中的导电图案并切割导电图案; 以及设置在贯通芯片通孔的外周面上的绝缘图案，以使导电图案与贯通芯片通孔绝缘。

16. 发明申请

US20120157015A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CONTROL SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：半导体器件和半导体控制系统，包括它们
公开(公告)号：US20120157015A1
公开(公告)日：2012-06-21
申请号：US13048283
申请日：2011-03-15
申请人： Jun-Gi CHOI , Jeong-Ho CHO , Hyung-Jun CHO
发明人： Jun-Gi CHOI , Jeong-Ho CHO , Hyung-Jun CHO
IPC分类号： H04B1/38 , H01Q1/38
CPC分类号： H04B1/40 , H01Q7/00 , H01Q23/00
摘要： A semiconductor device includes an interface pad, and an antenna formed to surround the interface pad. The semiconductor device may further include a buffer configured to receive a first input signal applied to the interface pad, a driver configured to output a first output signal to the interface pad a receiver configured to receive a second input signal transferred to the antenna, and a transmitter configured to output a second output signal to the antenna.
摘要翻译：半导体器件包括接口焊盘和形成为围绕接口焊盘的天线。半导体器件还可以包括缓冲器，其被配置为接收施加到接口焊盘的第一输入信号;驱动器，被配置为向接口焊盘输出第一输出信号，接收器被配置为接收传送到天线的第二输入信号，以及发射机被配置为向天线输出第二输出信号。

17. 发明授权

US08183898B2 Apparatus for supplying voltage free noise and method of operation the same 失效
标题翻译：用于提供无电压噪声的装置及其操作方法
公开(公告)号：US08183898B2
公开(公告)日：2012-05-22
申请号：US13180584
申请日：2011-07-12
申请人： Yoon-Jae Shin , Jun-Gi Choi
发明人： Yoon-Jae Shin , Jun-Gi Choi
IPC分类号： H03L7/00
CPC分类号： H03K17/145 , H03K19/00384 , Y10T307/696
摘要： A voltage supply apparatus includes a power noise sensing unit, a voltage selecting unit, a first power voltage supply unit and a second power voltage supply unit. The power noise sensing unit senses noise from first and second powers and outputs a power noise sensing signal. The voltage selecting unit outputs first and second driving signals in response to a voltage-supply-enable-signal and the power noise sensing signal. The first power voltage supply unit applies a voltage of the first power in response to the first and second driving signals. The second power voltage supply unit applies a voltage of the second power in response to the first and second driving signals.
摘要翻译：电压供给装置包括电源噪声检测单元，电压选择单元，第一电源电压单元和第二电源电压单元。功率噪声感测单元感测来自第一和第二功率的噪声，并输出功率噪声感测信号。电压选择单元响应于电压供应使能信号和功率噪声感测信号输出第一和第二驱动信号。第一电源电压单元响应于第一和第二驱动信号施加第一功率的电压。第二电源电压单元响应于第一和第二驱动信号施加第二功率的电压。

18. 发明申请

US20110291229A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US20110291229A1
公开(公告)日：2011-12-01
申请号：US12831341
申请日：2010-07-07
申请人： Sang-Jin BYEON , Jun-Gi Choi
发明人： Sang-Jin BYEON , Jun-Gi Choi
IPC分类号： H01L23/538 , H01L23/525 , H01L21/66
CPC分类号： H01L21/76879 , H01L23/481 , H01L23/5256 , H01L25/0657 , H01L2225/06527 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.
摘要翻译：半导体集成电路包括：半导体芯片; 通过芯片穿过设置在半导体芯片中的导电图案并切割导电图案; 以及设置在贯通芯片通孔的外周面上的绝缘图案，以使导电图案与贯通芯片通孔绝缘。

19. 发明申请

US20110272790A1 SEMICONDUCTOR CHIP AND SEMICONDUCTOR WAFER 有权
标题翻译：半导体芯片和半导体晶片
公开(公告)号：US20110272790A1
公开(公告)日：2011-11-10
申请号：US12833672
申请日：2010-07-09
申请人： Jun-Gi Choi , Jong-Chern Lee
发明人： Jun-Gi Choi , Jong-Chern Lee
IPC分类号： H01L23/544
CPC分类号： H01L22/32 , H01L22/34 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.
摘要翻译：半导体晶片包括形成在基板上的至少一个芯片和围绕芯片的划线区域。芯片包括器件形成区域和围绕器件形成区域并形成在器件形成区域和划线区域之间的芯片边界区域。芯片边界区域包括将器件形成区域与划线区域物理分离的保护环结构。保护环结构包括在器件形成区域和划线区域之间传送电信号的信号传输元件。

20. 发明申请

US20110234303A1 ELECTRIC FUSE CIRCUIT AND METHOD OF OPERATING THE SAME 有权
标题翻译：电保险丝电路及其操作方法
公开(公告)号：US20110234303A1
公开(公告)日：2011-09-29
申请号：US12841106
申请日：2010-07-21
申请人： Jun Gi CHOI
发明人： Jun Gi CHOI
IPC分类号： H01H37/76
CPC分类号： H01L23/5256 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A fuse circuit includes an electric fuse coupled to a first voltage source; a low resistance unit coupled to the electric fuse and having a junction which is capable of breaking down; and a switching unit coupled between the low resistance unit and a second voltage source.
摘要翻译：熔丝电路包括耦合到第一电压源的电熔丝; 耦合到电熔丝并具有能够分解的结的低电阻单元; 以及耦合在所述低电阻单元和第二电压源之间的开关单元。

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