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11. 发明申请

US20050237806A1 Circuit and method for detecting skew of transistor in semiconductor device 失效
标题翻译：用于检测半导体器件中晶体管的偏斜的电路和方法
公开(公告)号：US20050237806A1
公开(公告)日：2005-10-27
申请号：US11019395
申请日：2004-12-23
申请人： Hwang Hur , Jun-Gi Choi
发明人： Hwang Hur , Jun-Gi Choi
IPC分类号： G11C7/00 , G11C16/04 , G11C29/50
CPC分类号： G11C29/50 , G11C29/12005 , G11C2029/5002
摘要： A circuit and method for easily detecting skew of a transistor within a semiconductor device are provided. The circuit for detecting the skew of the transistor includes a linear voltage generating unit for outputting a linear voltage by using a first supply voltage, a first attenuation unit for reducing variation width of the linear voltage according to the performance of the transistor, a saturation voltage generating unit for outputting a saturation voltage by using a second supply voltage, and a comparison unit for comparing an output of the first attenuation unit and the saturation voltage.
摘要翻译：提供一种用于容易地检测半导体器件内的晶体管的偏斜的电路和方法。用于检测晶体管的偏斜的电路包括用于通过使用第一电源电压输出线性电压的线性电压产生单元，用于根据晶体管的性能减小线性电压的变化幅度的第一衰减单元，饱和电压产生单元，用于通过使用第二电源电压输出饱和电压;以及比较单元，用于比较第一衰减单元的输出和饱和电压。

12. 发明申请

US20050206430A1 Skew detection device 有权
标题翻译：偏斜检测装置
公开(公告)号：US20050206430A1
公开(公告)日：2005-09-22
申请号：US10878444
申请日：2004-06-28
申请人： Jun Gi Choi
发明人： Jun Gi Choi
IPC分类号： G11C8/00 , G01R31/26 , H03L5/00
CPC分类号： G01R31/2621 , G01R31/2628
摘要： The present invention discloses a skew detection device which can detect a skew of a transistor changed due to a driving voltage, a size and a process variable. The skew detection device includes a first potential level generator for outputting a first voltage, a second potential level generator for outputting a second voltage, a first level shifter for receiving the first voltage and outputting a first shift voltage, a second level shifter for receiving the second voltage and outputting a second shift voltage, and a comparator for comparing the first shift voltage with the second shift voltage. The first voltage is determined according to a drain-source current of a first MOS transistor operated in a linear region, and the second voltage is determined according to a drain-source current of a second MOS transistor operated in a saturation region.
摘要翻译：本发明公开了一种可以检测由于驱动电压，尺寸和过程变量而改变的晶体管的偏斜的偏斜检测装置。偏斜检测装置包括用于输出第一电压的第一电位电平发生器，用于输出第二电压的第二电位电平发生器，用于接收第一电压并输出第一移位电压的第一电平移位器，用于接收第一电压的第二电平移位器第二电压并输出第二移位电压;以及比较器，用于将第一移位电压与第二移位电压进行比较。根据在线性区域中工作的第一MOS晶体管的漏 - 源电流来确定第一电压，并且根据在饱和区域中操作的第二MOS晶体管的漏 - 源电流来确定第二电压。

13. 发明授权

US06751134B2 Internal voltage generating apparatus for a semiconductor memory device 有权
标题翻译：一种用于半导体存储器件的内部电压产生装置
公开(公告)号：US06751134B2
公开(公告)日：2004-06-15
申请号：US10330887
申请日：2002-12-27
申请人： Jun Gi Choi , Tae Yun Kim
发明人： Jun Gi Choi , Tae Yun Kim
IPC分类号： G11C700
CPC分类号： G11C29/12005 , G11C11/401 , G11C11/4074 , G11C29/12 , G11C2207/105
摘要： An internal voltage generating apparatus for a semiconductor memory device is described herein. The internal voltage generating apparatus is configured to execute an internal voltage margin test with a small number of pads by installing a forcing pad and fuse (or switch) in an initial reference voltage generating terminal during a multi-chip product test of the DRAM to cut down expenses, and to overcome load or noise due to the forcing pad by cutting (switching off) the fuse after a wafer level test during a normal operation.
摘要翻译：本文描述了一种用于半导体存储器件的内部电压产生装置。内部电压发生装置被配置为通过在DRAM的多芯片产品测试期间将迫击焊盘和熔丝（或开关）安装在初始参考电压产生端子中来执行具有少量焊盘的内部电压裕度测试并且在正常操作期间通过在晶圆级测试之后切断（断开）熔断器来克服由于强迫焊盘引起的负载或噪声。

14. 发明授权

US06333249B2 Method for fabricating a semiconductor device 失效
公开(公告)号：US06333249B2
公开(公告)日：2001-12-25
申请号：US09751941
申请日：2001-01-02
申请人： Seon Soon Kim , Jun Gi Choi
发明人： Seon Soon Kim , Jun Gi Choi
IPC分类号： H01L213205
CPC分类号： H01L27/10894 , H01L21/823842 , H01L27/10873
摘要： A method for fabricating a semiconductor device is disclosed. In a process for fabricating a CMOS transistor of a high integrated semiconductor device and a cell of a DRAM, a process for forming a dual gate electrode having a layered structure of a tungsten layer and a polysilicon layer includes the steps of forming a gate electrode shape from an undoped polysilicon layer, forming an insulating film spacer at sidewalls of the polysilicon layer, forming an LDD region, removing a portion of the undoped polysilicon layer to leave a predetermined thickness and to form an opening in which the tungsten layer will be formed, and respectively implanting different impurity ions into the undoped polysilicon layer respectively formed in the PMOS region and the NMOS region before forming the tungsten layer. Thus, it is possible to prevent etching residue from occurring and also prevent the semiconductor substrate from being damaged. In addition, it is possible to prevent the tungsten layer from being oxidized due to a high temperature process such as an ion plantation process for forming the LDD region and the source/drain region, thereby improving operational characteristics of the device and process yield.

15. 发明授权

US08477521B2 Fuse circuit and memory device including the same 有权
标题翻译：保险丝电路和包括其的存储器件
公开(公告)号：US08477521B2
公开(公告)日：2013-07-02
申请号：US12981290
申请日：2010-12-29
申请人： Kwi-Dong Kim , Jun-Gi Choi
发明人： Kwi-Dong Kim , Jun-Gi Choi
IPC分类号： G11C17/00 , G11C7/00 , G11C17/18 , G11C8/00
CPC分类号： G11C17/165 , G11C17/18 , G11C29/787
摘要： A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.
摘要翻译：熔丝电路包括多个熔丝单元，放大单元和多个寄存器。放大单元被配置为顺序放大存储在熔丝单元中的数据。寄存器被配置为顺序地存储由放大单元放大的数据。

16. 发明授权

US08421520B2 Electric fuse circuit and method of operating the same 有权
标题翻译：电熔丝电路及其操作方法
公开(公告)号：US08421520B2
公开(公告)日：2013-04-16
申请号：US12841106
申请日：2010-07-21
申请人： Jun Gi Choi
发明人： Jun Gi Choi
IPC分类号： G01R31/28
CPC分类号： H01L23/5256 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A fuse circuit includes an electric fuse coupled to a first voltage source; a low resistance unit coupled to the electric fuse and having a junction which is capable of breaking down; and a switching unit coupled between the low resistance unit and a second voltage source.
摘要翻译：熔丝电路包括耦合到第一电压源的电熔丝; 耦合到电熔丝并具有能够分解的结的低电阻单元; 以及耦合在所述低电阻单元和第二电压源之间的开关单元。

17. 发明申请

US20120092947A1 FUSE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：保险丝电路和包括其的存储器件
公开(公告)号：US20120092947A1
公开(公告)日：2012-04-19
申请号：US12981290
申请日：2010-12-29
申请人： Kwi-Dong KIM , Jun-Gi CHOI
发明人： Kwi-Dong KIM , Jun-Gi CHOI
IPC分类号： G11C17/16
CPC分类号： G11C17/165 , G11C17/18 , G11C29/787
摘要： A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.
摘要翻译：熔丝电路包括多个熔丝单元，放大单元和多个寄存器。放大单元被配置为顺序放大存储在熔丝单元中的数据。寄存器被配置为顺序地存储由放大单元放大的数据。

18. 发明申请

US20120057413A1 SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF 有权
标题翻译：半导体存储器及其测试方法
公开(公告)号：US20120057413A1
公开(公告)日：2012-03-08
申请号：US12948874
申请日：2010-11-18
申请人： Tae Sik YUN , Hyung Dong Lee , Jun Gi Choi , Sang Jin Byeon , Sang Hoon Shin
发明人： Tae Sik YUN , Hyung Dong Lee , Jun Gi Choi , Sang Jin Byeon , Sang Hoon Shin
IPC分类号： G11C8/18 , G11C29/00 , G11C7/10 , G11C7/22
CPC分类号： G11C7/22 , G11C7/222 , G11C29/006 , G11C29/023
摘要： A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.
摘要翻译：一种半导体存储装置，包括：时钟控制单元，被配置为当使能信号被激活时接收第一时钟，并产生具有与第一时钟相对于目标时钟周期更长的周期的第二时钟; DLL输入时钟生成单元，被配置为根据DLL选择信号将第一时钟和第二时钟中的一个作为DLL输入时钟输出; 以及地址/命令输入时钟生成单元，被配置为根据使能信号将第一时钟和第二时钟中的一个作为AC输入时钟输出。

19. 发明申请

US20110246104A1 SEMICONDUCTOR APPARATUS AND CHIP SELECTING METHOD THEREOF 审中-公开
标题翻译：半导体器件和芯片选择方法
公开(公告)号：US20110246104A1
公开(公告)日：2011-10-06
申请号：US12839356
申请日：2010-07-19
申请人： Jae Bum KO , Jun Gi CHOI
发明人： Jae Bum KO , Jun Gi CHOI
IPC分类号： G06F19/00
CPC分类号： G11C8/12 , G11C29/785 , G11C29/883 , H01L2225/06527
摘要： A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals.
摘要翻译：一种半导体装置，包括单独的芯片指定代码设置块，其被配置为生成不同值的多个独立芯片指定代码; 单个芯片激活块，其被配置为当各个芯片指定代码与单独的芯片控制代码匹配时，使多个独立芯片激活信号中的各个芯片激活信号对应于各个芯片指定代码; 以及控制块，被配置为响应于芯片选择熔丝信号和测试熔丝信号，将单独的芯片控制代码或输出芯片选择地址设置为单独的芯片控制代码。

20. 发明授权

US07973590B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07973590B2
公开(公告)日：2011-07-05
申请号：US12615876
申请日：2009-11-10
申请人： Sang-Hoon Shin , Hyung-Dong Lee , Jun-Gi Choi
发明人： Sang-Hoon Shin , Hyung-Dong Lee , Jun-Gi Choi
IPC分类号： H01H85/00
CPC分类号： H01L23/5256 , G11C17/16 , G11C17/18 , H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.
摘要翻译：半导体器件包括：第一传输线和布置在不同层的第二传输线; 与第一传输线和第二传输线耦合的接触熔丝; 功率驱动器，被配置为向所述接触保险丝施加电应力; 以及熔丝状态输出单元，被配置为输出具有与所述接触熔丝的电连接状态对应的逻辑电平的熔丝状态信号。

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