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1. 发明授权

US09142319B2 Semiconductor device employing fuse programming 有权
标题翻译：采用熔丝编程的半导体器件
公开(公告)号：US09142319B2
公开(公告)日：2015-09-22
申请号：US13595615
申请日：2012-08-27
申请人： Kwi-Dong Kim
发明人： Kwi-Dong Kim
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18 , G11C17/16
摘要： A semiconductor device includes a fuse unit connected to a detection node and configured to be programmed in response to a first voltage supplied through the detection node, an output unit connected to the detection node and configured to output a fuse information signal indicating whether the fuse unit is programmed or not, and a blocking unit configured to block the first voltage supplied through the detection node in response to the fuse information signal.
摘要翻译：半导体器件包括连接到检测节点并被配置为响应于通过检测节点提供的第一电压被编程的熔丝单元，连接到检测节点的输出单元，并且被配置为输出指示熔丝单元被配置为阻止响应于熔丝信息信号通过检测节点提供的第一电压的阻塞单元。

2. 发明授权

US08634265B2 Semiconductor memory device and method for operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08634265B2
公开(公告)日：2014-01-21
申请号：US12814702
申请日：2010-06-14
申请人： Kwi-Dong Kim , Ki-Chang Kwean
发明人： Kwi-Dong Kim , Ki-Chang Kwean
IPC分类号： G11C17/18
CPC分类号： G11C16/16 , G11C16/18
摘要： A semiconductor memory device including an information storage unit comprising a fuse configured to store information, a control unit configured to control a node of a blown fuse to become a floating state in response to a control pulse signal, and an output unit configured to output the information.
摘要翻译：一种半导体存储器件，包括：信息存储单元，包括被配置为存储信息的熔丝;控制单元，被配置为响应于控制脉冲信号控制熔断熔丝的节点变为浮置状态;以及输出单元，信息。

3. 发明授权

US08446194B2 Spread spectrum clock generating circuit 有权
标题翻译：扩频时钟发生电路
公开(公告)号：US08446194B2
公开(公告)日：2013-05-21
申请号：US13275753
申请日：2011-10-18
申请人： Seok Ju Yun , Hui Dong Lee , Kwi Dong Kim , Jong-Kee Kwon
发明人： Seok Ju Yun , Hui Dong Lee , Kwi Dong Kim , Jong-Kee Kwon
IPC分类号： H03L7/06
CPC分类号： H03L7/1976 , H03L7/0891
摘要： Provided is a spread spectrum clock generating circuit. The spread spectrum clock generating circuit includes: a phase detector receiving a reference frequency signal from the external and detecting a phase difference between the reference frequency signal and a frequency-divided signal; a voltage controlled oscillator outputting an oscillation signal corresponding to a detection result of the phase detector; a main divider generating the frequency-divided signal by dividing a frequency of the oscillation signal by a main dividing ratio; and a dividing ratio controller generating a variable count value, generating a sub dividing ratio by performing delta-sigma modulation according to the count value, and adjusting the main dividing ratio according to the sub dividing ratio.
摘要翻译：提供了一种扩频时钟发生电路。扩频时钟发生电路包括：相位检测器，从外部接收参考频率信号，并检测参考频率信号与分频信号之间的相位差; 输出与所述相位检测器的检测结果对应的振荡信号的压控振荡器; 主分压器，通过将振荡信号的频率除以主分频比来产生分频信号; 以及产生可变计数值的分频比控制器，通过根据计数值进行Δ-Σ调制而产生分分割比，并根据分分割比调节主分频比。

4. 发明申请

US20120105114A1 SPREAD SPECTRUM CLOCK GENERATING CIRCUIT 有权
标题翻译：传播频谱时钟发生电路
公开(公告)号：US20120105114A1
公开(公告)日：2012-05-03
申请号：US13275753
申请日：2011-10-18
申请人： Seok Ju YUN , Hui Dong Lee , Kwi Dong Kim , Jong-Kee Kwon
发明人： Seok Ju YUN , Hui Dong Lee , Kwi Dong Kim , Jong-Kee Kwon
IPC分类号： H03L7/06
CPC分类号： H03L7/1976 , H03L7/0891
摘要： Provided is a spread spectrum clock generating circuit. The spread spectrum clock generating circuit includes: a phase detector receiving a reference frequency signal from the external and detecting a phase difference between the reference frequency signal and a frequency-divided signal; a voltage controlled oscillator outputting an oscillation signal corresponding to a detection result of the phase detector; a main divider generating the frequency-divided signal by dividing a frequency of the oscillation signal by a main dividing ratio; and a dividing ratio controller generating a variable count value, generating a sub dividing ratio by performing delta-sigma modulation according to the count value, and adjusting the main dividing ratio according to the sub dividing ratio.
摘要翻译：提供了一种扩频时钟发生电路。扩频时钟发生电路包括：相位检测器，从外部接收参考频率信号，并检测参考频率信号与分频信号之间的相位差; 输出与所述相位检测器的检测结果对应的振荡信号的压控振荡器; 主分压器，通过将振荡信号的频率除以主分频比来产生分频信号; 以及产生可变计数值的分频比控制器，通过根据计数值进行Δ-Σ调制而产生分分割比，并根据分分割比调节主分频比。

5. 发明授权

US08111574B2 Circuit and method for controlling self-refresh cycle 有权
标题翻译：控制自刷新周期的电路和方法
公开(公告)号：US08111574B2
公开(公告)日：2012-02-07
申请号：US12535069
申请日：2009-08-04
申请人： Kwi Dong Kim
发明人： Kwi Dong Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40615 , G11C11/40626 , G11C2211/4061 , G11C2211/4068
摘要： The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or not a voltage charged into a capacitor of a detection cell drops to or below a reference voltage and outputs a detection signal. A pulse generator generates a self-refresh pulse while being linked with an enabled detection signal of the plurality of detectors. A self-refresh cycle can be variably controlled and set to be suitable for the charging capacity of a cell. The detection cell is adapted to the change of the charging capacity of the cell in accordance with a change in temperature.
摘要翻译：本发明涉及用于控制动态随机存取存储器或DRAM的自刷新周期的电路和方法。直接检测电池电压，使得可以可变地控制自刷新周期。检测器各自检测充电到检测单元的电容器中的电压是否下降到或低于参考电压，并输出检测信号。脉冲发生器在与多个检测器的使能检测信号链接的同时产生自刷新脉冲。自刷新周期可以被可变地控制并且设置成适合于电池的充电容量。检测单元根据温度的变化适应电池的充电容量的变化。

6. 发明授权

US08081038B2 Ring oscillator having wide frequency range 有权
标题翻译：振铃频率范围宽
公开(公告)号：US08081038B2
公开(公告)日：2011-12-20
申请号：US12507687
申请日：2009-07-22
申请人： Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon
发明人： Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K2005/00045 , H03K2005/00058 , H03L7/0995
摘要： Provided is a ring oscillator having an extended range of oscillation frequency by varactors coupled to delay cells even in a simple structure. The wide frequency range results from simply varying an oscillation frequency by control signals applied to the varactors. Since additional switches connected to the delay cells contribute to increase or decrease of the oscillation frequency range, the ring oscillator can conveniently be employed in various types of oscillation systems.
摘要翻译：提供一种环形振荡器，即使在简单的结构中，也可以通过连接到延迟单元的变容二极管具有扩展的振荡频率范围。宽频率范围是通过施加到变容二极管的控制信号简单地改变振荡频率。由于连接到延迟单元的附加开关有助于振荡频率范围的增加或减少，因此环形振荡器可以方便地用于各种类型的振荡系统。

7. 发明申请

US20100156542A1 LOW VOLTAGE FREQUENCY SYNTHESIZER USING BOOSTING METHOD FOR POWER SUPPLY VOLTAGE OF CHARGE PUMP 失效
标题翻译：使用充电泵电源电压升压方法的低电压频率合成器
公开(公告)号：US20100156542A1
公开(公告)日：2010-06-24
申请号：US12561910
申请日：2009-09-17
申请人： Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon , Jong Pil Hong , Sang Gug Lee
发明人： Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon , Jong Pil Hong , Sang Gug Lee
IPC分类号： H03L7/08
CPC分类号： H03L7/0891 , H03L5/00 , H03L7/099
摘要： Provided is a low voltage frequency synthesizer using a boosting method for a power supply voltage of a charge pump. The low voltage frequency synthesizer includes a phase/frequency detector (PFD) that receives and compares a reference frequency and a feedback frequency to output a comparison signal, a charge pump that receives the comparison signal to output a current corresponding to the comparison signal, a low-pass filter (LPF) that generates a voltage corresponding to the output current of the charge pump, a voltage controlled oscillator (VCO) that receives the voltage of the LPF, amplifies the voltage to generate a boosting voltage, and outputs a frequency corresponding to the received voltage, and a DC converter that receives the boosting voltage of the VCO, converts the boosting voltage into a DC voltage, and applies the DC voltage as a power supply voltage of the charge pump. Since the supply voltage of the charge pump is provided from the LC-circuit-based VCO, the frequency synthesizer has superior characteristics such as a wide locking range, low phase noise, and the prevention of performance degradation caused by an external environment or process variations.
摘要翻译：提供了使用电荷泵的电源电压的升压方法的低压频率合成器。所述低电压频率合成器包括接收比较参考频率和反馈频率以输出比较信号的相位/频率检测器（PFD），接收比较信号以输出与比较信号相对应的电流的电荷泵，产生与电荷泵的输出电流相对应的电压的低通滤波器（LPF），接收LPF电压的压控振荡器（VCO），放大电压以产生升压电压，并输出对应的频率以及接收VCO的升压电压的DC转换器，将升压电压转换成直流电压，并施加直流电压作为电荷泵的电源电压。由于电荷泵的电源电压是从基于LC电路的VCO提供的，因此频率合成器具有优异的特性，例如宽锁定范围，低相位噪声，以及防止由外部环境或工艺变化引起的性能下降。

8. 发明授权

US07511581B2 Wide-band multimode frequency synthesizer and variable frequency divider 有权
标题翻译：宽带多模频率合成器和可变分频器
公开(公告)号：US07511581B2
公开(公告)日：2009-03-31
申请号：US11634004
申请日：2006-12-05
申请人： Ja Yol Lee , Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim , Sang Heung Lee
发明人： Ja Yol Lee , Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim , Sang Heung Lee
IPC分类号： H03L7/00
CPC分类号： H03K23/667 , H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/193
摘要： A wide-band multimode frequency synthesizer using a Phase Locked Loop (PLL) is provided. The multiband frequency synthesizer includes a multimode prescaler, a phase detector/a charge pump, a swallow type frequency divider, and a switching bank LC tuning voltage-controlled oscillator having wide-band and low phase noise characteristics. The multimode prescaler operates in five modes and divides a signal up to 12 GHz. The wide-band frequency synthesizer can be used in various fields such as WLAN/HYPERLAN/DSRC/UWB systems that operate in the frequency range from 2 GHz to 9 GHz. The wide-band multimode frequency synthesizer includes a frequency/phase detector for comparing a frequency and phase of a reference high-frequency signal with a frequency and phase of a feedback high-frequency signal; a charge pump for producing an output current corresponding to the result of the comparison performed by the frequency/phase detector; a loop filter for producing an output voltage corresponding to an accumulated value of the output current of the charge pump; a voltage-controlled oscillator for generating an oscillation signal having a frequency corresponding to the output voltage of the loop filter; and a variable frequency divider for dividing an output signal of the voltage-controlled oscillator by a designated integer value, and outputting the result as a feedback signal, wherein at lease two of an amount of unit pumping charges of the charge pump, an RLC value of the loop filter, an RLC value of the voltage-controlled oscillator, and a divisor value of the variable frequency divider are controlled according to a band.
摘要翻译：提供了使用锁相环（PLL）的宽带多模频率合成器。多频率频率合成器包括多模预分频器，相位检测器/电荷泵，燕子式分频器和具有宽带和低相位噪声特性的开关组LC调谐压控振荡器。多模预分频器以五种模式工作，并将信号分为12 GHz。宽带频率合成器可用于各种领域，例如在2 GHz至9 GHz频率范围内工作的WLAN / HYPERLAN / DSRC / UWB系统。宽带多模频率合成器包括用于将参考高频信号的频率和相位与反馈高频信号的频率和相位进行比较的频率/相位检测器; 用于产生与由频率/相位检测器执行的比较结果相对应的输出电流的电荷泵; 环路滤波器，用于产生与电荷泵的输出电流的累积值相对应的输出电压; 用于产生具有与环路滤波器的输出电压对应的频率的振荡信号的压控振荡器; 以及可变分频器，用于将压控振荡器的输出信号除以指定的整数值，并输出该结果作为反馈信号，其中至少两个电荷泵的单位泵送电荷，RLC值根据频带控制环路滤波器的电压控制振荡器的RLC值和可变分频器的除数值。

9. 发明申请

US20080136693A1 MULTI-BIT DELTA-SIGMA MODULATOR 有权
标题翻译：多位三角形调制器
公开(公告)号：US20080136693A1
公开(公告)日：2008-06-12
申请号：US11950481
申请日：2007-12-05
申请人： Yi Gyeong KIM , Kwi Dong KIM , Chong Ki KWON , Jong Dae KIM
发明人： Yi Gyeong KIM , Kwi Dong KIM , Chong Ki KWON , Jong Dae KIM
IPC分类号： H03M3/00
CPC分类号： H03M3/374 , H03M3/338 , H03M3/424 , H03M3/45 , H03M3/452 , H03M3/454
摘要： Provided is a delta-sigma modulator including: a first integrator for integrating an input signal; an analog-to-digital converter for converting the integrated signal into a digital signal; and delay circuit for delaying an output signal of the analog-to-digital converter; and a differential delay circuit for differentially delaying the output signal of the analog-to-digital converter.
摘要翻译：提供一种Δ-Σ调制器，包括：用于对输入信号进行积分的第一积分器; 用于将积分信号转换为数字信号的模拟 - 数字转换器; 以及用于延迟模数转换器的输出信号的延迟电路; 以及用于差分地延迟模数转换器的输出信号的差分延迟电路。

10. 发明申请

US20080136464A1 METHOD OF FABRICATING BIPOLAR TRANSISTORS AND HIGH-SPEED LVDS DRIVER WITH THE BIPOLAR TRANSISTORS 审中-公开
标题翻译：用双极晶体管制作双极晶体管和高速LVDS驱动器的方法
公开(公告)号：US20080136464A1
公开(公告)日：2008-06-12
申请号：US11933025
申请日：2007-10-31
申请人： Kwi Dong KIM , Chong Ki Kwon , Jong Dae Kim
发明人： Kwi Dong KIM , Chong Ki Kwon , Jong Dae Kim
IPC分类号： H03K3/00 , H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/41708 , H01L29/7322 , H03F3/45085 , H03F3/45179 , H03F3/45502 , H03F2203/45008 , H03F2203/45082 , H03F2203/45418 , H03F2203/45424 , H03K5/003 , H03K19/01 , H04L25/0276 , H04L25/0282
摘要： Provided is a differential signal driver capable of operating at a high speed at a low voltage of 1.8V. The differential signal driver includes: a differential-signal driving circuit for switching input differential signals and outputting a common mode voltage through first and second output nodes; and a common-mode feedback circuit for providing a predetermined current to the differential-signal driving circuit or receiving a predetermined current from the differential-signal driving circuit in response to the common mode voltage. The differential-signal driving circuit includes a common-mode voltage output circuit for connecting the first output node to the second output node and generating the common mode voltage of the differential-signal driving circuit. The differential input signals are received through two bipolar transistors.
摘要翻译：提供能够以1.8V的低电压高速运行的差分信号驱动器。差分信号驱动器包括：差分信号驱动电路，用于切换输入差分信号并通过第一和第二输出节点输出共模电压; 以及共模反馈电路，用于响应于共模电压，向差分信号驱动电路提供预定电流或从差分信号驱动电路接收预定电流。差分信号驱动电路包括用于将第一输出节点连接到第二输出节点并产生差动信号驱动电路的共模电压的共模电压输出电路。差分输入信号通过两个双极晶体管接收。

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